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* AVR(R) RISC * AVR - RISC
- 120 - - 32 8 - - 20 MHz 20 MIPS - 2K Flash : 10,000 - 128 EEPROM : 100,000 - 128 SRAM - EEPROM - 8 / - 16 / - PWM - - - USI - - USART - debugWIRE - SPI - / - Standby - - - I/O - 18 I/O - 20 PDIP, 20 SOIC 32 MLF - 1.8 - 5.5V (ATTINY2313V) - 2.7 - 5.5V (ATtiny2313) - ATTINY2313V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V - ATtiny2313: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V - : 1 MHz, 1.8V: 300 A 32 kHz, 1.8V: 20 A ( ) - : < 0.2 A at 1.8V
*
*
2KB Flash 8 ATtiny2313/V
*
* * * *
Rev. 2543F-AVR-07/04
Figure 1. ATtiny2313
PDIP/SOIC
(RESET/dW)PA2 (RXD)PD0 (TXD)PD1 (XTAL2)PA1 (XTAL1)PA0 (CKOUT/XCK/INT0)PD2 (INT1)PD3 (T0)PD4 (OC0B/T1)PD5 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC PB7(UCSK/SCK/PCINT7) PB6(MISO/DO/PCINT6) PB5(MOSI/DI/SDA/PCINT5) PB4(OC1B/PCINT4) PB3(OC1A/PCINT3) PB2(OC0A/PCINT2) PB1(AIN1/PCINT1) PB0(AIN0/PCINT0) PD6(ICP)
ATtiny2313 AVR RISC 8 CMOS ATtiny2313 1 MIPS/MHz
2
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ATtiny2313/V
Figure 2.
XTAL1 PA0 - PA2
XTAL2
PORTA DRIVERS
VCC
DATA REGISTER PORTA
DATA DIR. REG. PORTA
INTERNAL CALIBRATED OSCILLATOR
8-BIT DATA BUS GND PROGRAM COUNTER STACK POINTER
INTERNAL OSCILLATOR
OSCILLATOR
WATCHDOG TIMER MCU CONTROL REGISTER MCU STATUS REGISTER
TIMING AND CONTROL
RESET
PROGRAM FLASH
SRAM
ON-CHIP DEBUGGER
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTER
TIMER/ COUNTERS INTERRUPT UNIT
INSTRUCTION DECODER
EEPROM CONTROL LINES ALU USI STATUS REGISTER
PROGRAMMING LOGIC
SPI
USART
ANALOG COMPARATOR
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
PORTB DRIVERS
PORTD DRIVERS
PB0 - PB7
PD0 - PD6
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AVR 32 (ALU) CISC 10 ATtiny23132KFlash 128EEPROM 128SRAM18 I/O 32 2 / / USART CPU SRAM T/C Standby Atmel SPI 8 RISC CPU Flash ATtiny2313 ATtiny2313 AVR C /
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VCC GND A(PA2..PA0) A 3 I/O A A P51 B(PB7..PB0) B 8 I/O B B P51 D(PD6..PD0) D 7 I/O D D P54 RESET P32Table 15 PA2dW XTAL1 PA0 XTAL2 PA1 C C AVR
XTAL1 XTAL2
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AVR CPU

AVR CPU Figure 3. AVR
Data Bus 8-bit
Flash Program Memory
Program Counter
Status and Control
Instruction Register
32 x 8 General Purpose Registrers
Interrupt Unit SPI Unit Watchdog Timer
Indirect Addressing
Instruction Decoder
Direct Addressing
ALU
Control Lines
Analog Comparator
I/O Module1
Data SRAM
I/O Module 2
I/O Module n EEPROM
I/O Lines
AVR Harvard CPU ( ) Flash 32 8 ALU ALU 6 3 16 16 X Y Z
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ALU ALU / 16 16 32 (PC) SRAM SRAM SP I/O SRAM 5 AVR AVR I/O I/O64 CPUI/O 0x20 - 0x5F
ALU
AVR ALU 32 ALU ALU 3 / ALU
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AVR SREG
Bit / 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG
* Bit 7 - I: I I I RETI I I SEI CLI * Bit 6 - T: BLD BST T BST T BLD T * Bit 5 - H: H BCD * Bit 4 - S: , S = N
V
S N 2 V * Bit 3 - V: 2 2 * Bit 2 - N: * Bit 1 - Z: * Bit 0 - C:
AVR RISC / * * * * 8 8 8 8 8 16 16 16
Figure 4 CPU 32 Figure 4. AVR CPU
7 R0 R1 R2 ... R13 R14 R15 R16 0x0D 0x0E 0x0F 0x10 0 Addr. 0x00 0x01 0x02
8
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ATtiny2313/V
R17 ... R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X X Y Y Z Z 0x11
Figure 4 32 SRAM X Y Z XYZ R26..R31 Figure 5 Figure 5. X Y Z
15 X 7 R27 (0x1B) XH 0 7 R26 (0x1A) XL 0 0
15 Y 7 R29 (0x1D) 15 Z 7 R31 (0x1F)
YH 0 7 R28 (0x1C) ZH 0 7 R30 (0x1E)
YL
0 0
ZL 0
0

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/ AVR SRAM 0x60 PUSH POP RET RETI AVRI/O8 AVR SPL SPH
Bit 15 - SP7 7 / R R/W 0 0 14 - SP6 6 R R/W 0 0 13 - SP5 5 R R/W 0 0 12 - SP4 4 R R/W 0 0 11 - SP3 3 R R/W 0 0 10 - SP2 2 R R/W 0 0 9 - SP1 1 R R/W 0 0 8 - SP0 0 R R/W 0 0 SPH SPL
AVR CPU clkCPU Figure 6 Harvard 1 MIPS/MHz / / Figure 6.
T1 T2 T3 T4
clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
Figure 7 ALU
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Figure 7. ALU
T1 T2 T3 T4
clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back
AVR I P42" " RESET INT0 - 0 P42" " I I RETI I "1" "0" I AVR CLI CLI CLI EEPROM EEPROM
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in r16, SREG cli ; sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16
; SREG ; EEPROM ; SREG (I )
C
char cSREG; cSREG = SREG; /* SREG */ /* */ __disable_interrupt(); EECR |= (1< SEI
sei ; sleep ; ; : MCU
C
_SEI(); /* */ _SLEEP(); /* */ /* : MCU */
AVR 4 4 4 PC 3 MCU MCU 4 4 PC( ) SREG I
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ATtiny2313/V
AVR ATtiny2313
ATtiny2313 AVR ATtiny2313 EEPROM
Flash ATtiny2313 2K Flash AVR 16 32 Flash 1K x 16
Flash10,000 ATtiny2313(PC)10 1K P150" " SPI Flash ( LPM ) P10" " Figure 8.
Program Memory 0x0000
0x03FF
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SRAM
Figure 9 ATtiny2313 SRAM 224 I/O I/O SRAM 3264I/O 128SRAM 5 R26 R31 Y Z 63 X Y Z ATtiny231332 64I/O128SRAM P8" " Figure 9.
Data Memory
32 Registers 64 I/O Registers 0x0000 - 0x001F 0x0020 - 0x005F 0x0060
Internal SRAM (128 x 8) 0x00DF
Figure 10 SRAM clkCPU Figure 10. SRAM
T1 T2 T3
clkCPU Address Data WR Data RD
Compute Address Address valid
Memory Access Instruction
Next Instruction
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Read
Write
ATtiny2313/V
EEPROM
ATtiny2313 128 EEPROM EEPROM 100,000 EEPROM EEPROM EEPROM I/O EEPROM Table 1 EEPROM / VCC / CPU P19 " EEPROM " EEPROM EEPROM EEPROM EEPROM CPU 4 EEPROM CPU 2 EEPROM
Bit / 7 - R 0 6 EEAR6 R/W X 5 EEAR5 R/W X 4 EEAR4 R/W X 3 EEAR3 R/W X 2 EEAR2 R/W X 1 EEAR1 R/W X 0 EEAR0 R/W X EEAR
EEPROM /
* Bit 7 - Res:
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* Bits 6..0 - EEAR6..0: EEPROM EEPROMEEARL128 EEPROM EEPROM 0 127 EEAR EEPROM EEPROM EEDR
Bit / 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 EEDR
* Bits 7..0 - EEDR7..0: EEPROM EEPROM EEDR EEAR EEDR EEARL EEPROM EECR
Bit / 7 - R 0 6 - R 0 5 EEPM1 R/W X 4 EEPM0 R/W X 3 EERIE R/W 0 2 EEMPE R/W 0 1 EEPE R/W X 0 EERE R/W 0 EECR
* Bits 7..6 - Res: * Bits 5, 4 - EEPM1 EEPM0: EEPROM EEPE ( ) Table 1 EEPE EEPMn EEPROM EEPMn 0b00 Table 1. EEPROM
EEPM1 0 0 1 1 EEPM0 0 1 0 1 3.4 ms 1.8 ms 1.8 ms -
* Bit 3 - EERIE: EEPROM SREG I "1" EERIE EEPROM EERIE EEPROM
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* Bit 2 - EEMPE: EEPROM EEMPE EEPE "1" EEMPE "1" EEPE EEPROM EEMPE "0" EEPE EEMPE "1" * Bit 1 - EEPE: EEPROM EEPE EEPROM EEPE "1" EEPMn EEPROM EEPE"1" EEMPE"1" EEPROM EEPE EEPE CPU * Bit 0 - EERE: EEPROM EEREEEPROM EEPROM EERE EEARL EEPROM EEPROM CPU 4 EEPROM EEPE EEPROM EEAR EEPROM EEARL EEDR EEPMn EEPE ( EEMPE ) / Table 1 EEPE EEPROM ( ) ( ) EEARL EEPMn 0b01 EEPE ( EEMPE ) ( Table 1) EEPE EEPROM EEARL EEDR EEPMn 0b10 EEPE ( EEMPE ) ( Table 1) EEPE EEPROM EEPROM P25"OSCCAL"
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C EEPROM
EEPROM_write: ; sbic EECR,EEPE rjmp EEPROM_write ; ldi out r16, (0<; r17 out EEARL, r17 ; (r16) out EEDR,r16 ; EEMWE sbi EECR,EEMWE ; EEWE sbi EECR,EEWE ret
C
void EEPROM_write(unsigned char ucAddress, unsigned char ucData) { /* */ while(EECR & (1<>EEPM0) /* */ EEARL = ucAddress; EEDR = ucData; /* EEMWE */ EECR |= (1<18
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C EEPROM
EEPROM_read: ; sbic EECR,EEPE rjmp EEPROM_read ; r17 out EEARL, r17 ; EERE sbi EECR,EERE ; in ret r16,EEDR
C
unsigned char EEPROM_read(unsigned char ucAddress) { /* */ while(EECR & (1< EEPROM
CPU EEPROM EEPROM ( ) EEPROM EEPROM EEPROM CPU EEPROM AVR RESET BOD BOD
I/O
ATtiny2313 I/O P202" " ATtiny2313I/OI/O I/OLD/LDS/LDD ST/STS/STD 32 I/O 0x00 - 0x1FI/OSBICBI SBISSBIC IN OUT 0x00 - 0x3F SRAM LD ST I/O 0x20 "0" I/O
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"1" AVR CBI SBI CBI SBI 0x00 0x1F I/O I/O ATtiny23133I/O 0x00 - 0x1F I/O SBI CBI SBIS SBIC
Bit / 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 GPIOR2
I/O 2 GPIOR2
I/O 1 GPIOR1
Bit /
7 MSB R/W 0
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 R/W 0
0 LSB R/W 0 GPIOR1
I/O 0 GPIOR0
Bit /
7 MSB R/W 0
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 R/W 0
0 LSB R/W 0 GPIOR0
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Figure 11AVR P29" " Figure 11 Figure 11.
General I/O Modules CPU Core RAM Flash and EEPROM
clkI/O
AVR Clock Control Unit
clkCPU clkFLASH
Reset Logic
Watchdog Timer
Source clock Clock Multiplexer
Watchdog clock
Watchdog Oscillator
External Clock
Crystal Oscillator
Calibrated RC Oscillator
CPU clkCPU I/O clkI/O
CPUAVR CPU I/O I/O / USART I/O I/O clkI/O USI USI Flash Flash CPU ATtiny2313Flash AVR Table 2. (1)
4MHz RC 8MHz RC CKSEL3..0 0000 0010 0100
Flash clkFLASH
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Table 2. (1)
128kHz Note: 1. "1" "0" CKSEL3..0 0000 0110 1000 - 1111 0001/0011/0101/0111
CPU CPU MCU WDT Table 3 P171"ATtiny2313 " Table 3.
(VCC = 5.0V) 4.1 ms 65 ms (VCC = 3.0V) 4.3 ms 69 ms 4K (4,096) 64K (65,536)
CKSEL = "0010" SUT = "10" CKDIV8 RC 8 ISP XTAL1 XTAL2 P22Figure 12 C1 C2 P23Table 4 Figure 12.
C2 C1
XTAL2 XTAL1 GND
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ATtiny2313/V
CKSEL3..1 Table 4 Table 4.
CKSEL3..1 100
(2)
(1) (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 -
C1 C2 (pF) - 12 - 22 12 - 22 12 - 22
101 110 111 Notes:
1. 2.
Table 5 CKSEL0 SUT1..0
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Table 5.
CKSEL0 0 0 0 0 1 1 1 1 Notes: SUT1..0 00 01 10 11 00 01 10 11 258 CK
(1)
(VCC = 5.0V) 14CK + 4.1 ms 14CK + 65 ms 14CK 14CK + 4.1 ms 14CK + 65 ms 14CK 14CK + 4.1 ms 14CK + 65 ms
BOD BOD
258 CK(1) 1K CK(2) 1K CK(2) 1K CK(2) 16K CK 16K CK 16K CK
1. 2.
RC
RC 8.0 MHz 3V 25C CKDIV8 8 CKDIV8 Table 6 CKSEL OSCCAL RC 3V25C 10% www.atmel.com/avr 2% P152" " Table 6. RC
CKSEL3..0 0010 - 0011 0100 - 0101 Note: 1. 4.0 MHz(1) 8.0 MHz
SUT Table 7 Table 7. RC
SUT1..0 00 6 CK (VCC = 5.0V) 14CK BOD
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Table 7. RC
SUT1..0 01 10(1) 11 Note: 1. 6 CK 6 CK (VCC = 5.0V) 14CK + 4.1 ms 14CK + 65 ms
OSCCAL
Bit /
7 - R
6 CAL6 R/W
5 CAL5 R/W
4 CAL4 R/W
3 CAL3 R/W
2 CAL2 R/W
1 CAL1 R/W
0 CAL0 R/W OSCCAL
* Bits 6..0 - CAL6..0: OSCCAL 0x7F EEPROM Flash EEPROM Flash 10% 8.0/4.0 MHz Table 8 MCU RC 2% OSCCAL 0x20 Table 8. RC
OSCCAL 0x00 0x3F 0x7F 50% 75% 100% 100% 150% 200%
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XTAL1 Figure 13 CKSEL "0000" Figure 13.
NC
XTAL2
EXTERNAL CLOCK SIGNAL
XTAL1
GND
SUT Table 10 Table 9.
CKSEL3..0 0000 - 0001 0 - 16 MHz
Table 10.
SUT1..0 00 01 10 11 6 CK 6 CK 6 CK (VCC = 5.0V) 14CK 14CK + 4.1 ms 14CK + 65 ms BOD
MCU 2% MCU
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128 kHz
The 128 kHz Internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3 V and 25C. This clock may be selected as the system clock by programming the CKSEL Fuses to "0110 - 0111".128 kHz 128 kHz 3V 25C CKSEL "0110 - 0111" Table 11 SUT Table 11. 128 kHz
SUT1..0 00 01 10 11 6 CK 6 CK 6 CK 14CK 14CK + 4 ms 14CK + 64 ms BOD
CLKPR
Bit /
7
CLKPCE
6
-
5
-
4
-
3
CLKPS3
2
CLKPS2
1
CLKPS1
0
CLKPS0 CLKPR
R/W 0
R 0
R 0
R 0
R/W
R/W
R/W
R/W
* Bit 7 - CLKPCE: CLKPCE "1" CLKPS CLKPR"0"CLKPCE CLKPCE CLKPS CLKPCE CLKPCE * Bits 3..0 - CLKPS3..0: 3 - 0 MCU Table 12 CLKPS 1. CLKPCE "1" CLKPR "0" 2. CLKPS CLKPCE "0" CKDIV8CLKPS CKDIV8 CLKPS"0000" CKDIV8 CLKPS "0011" 8 CLKPS CKDIV8 CKDIV8 Table 12.
CLKPS3 0 0 0 0 0 CLKPS2 0 0 0 0 1 CLKPS1 0 0 1 1 0 CLKPS0 0 1 0 1 0 1 2 4 8 16
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Table 12.
CLKPS3 0 0 0 1 1 1 1 1 1 1 1 CLKPS2 1 1 1 0 0 0 0 1 1 1 1 CLKPS1 0 1 1 0 0 1 1 0 0 1 1 CLKPS0 1 0 1 0 1 0 1 0 1 0 1 32 64 128 256
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MCU AVR MCUCR SE SLEEP ( Standby ) MCUCR SM1 SM0 Table 13 MCU 4 MCU SLEEP SRAM MCU P21Figure 11 ATtiny2313 MCU MCUCR
Bit / 7 PUD R 0 6 SM1 R/W 0 5 SE R/W 0 4 SM0 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR
* Bits 6, 4 - SM1..0: 1 0 Table 13 Table 13.
SM1 0 0 1 1 Note: SM0 0 1 1 0 Standby
1. Standby
* Bit 5 - SE: MCU SLEEP SE SLEEP SEMCU SE
SM1..0 00 SLEEP MCU CPU ADC / clkCPU clkFLASH MCU MCU ACSR ACD ADC
SM1..0 01 11 SLEEP MCU USI BOD USI INT0 MCU MCU P57" "
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CKSEL P21" "
Standby
SM1..0 10 SLEEP MCU Standby 6 Table 14.
INT0, INT1 SPM/EEPROM X
USI
clkFLASH
Standby Notes:
(1)
X
X
X X
(2) (2)
X X X
X
X
1. 2. INT0
AVR P141" " BOD BODLEVEL BOD P33" " BOD BOD P36" " P42" " I/O clkI/O P48" " VCC/2 VCC/2 DIDR P142" DIDR"
BOD
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I/O X
clkCPU
clkIO
ATtiny2313/V
AVR I/O JMP Figure 14 Table 15 I/O MCU SUT CKSEL P21" " The ATtiny2313 4 * * * * VPOT MCU RESET MCU VBOT MCU
Figure 14.
DATA BUS
MCU Status Register (MCUSR)
PORF BORF EXTRF WDRF
Power-on Reset Circuit
BODLEVEL [2..0] Pull-up Resistor
SPIKE FILTER
Brown-out Reset Circuit
Watchdog Oscillator
Clock Generator
CK
Delay Counters TIMEOUT
CKSEL[3:0] SUT[1:0]
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Table 15.
( ) VPOT ( )(2) VRST tRST Notes: RESET RESET TA = -40 - 85C VCC = 1.8 - 5.5V VCC = 1.8 - 5.5V 0.1 VCC 1.1 0.9 VCC 2.5 V V s TA = -40 - 85C
(1)
(1)
(1)
V
1.2
1. 2. VPOT
(POR) Table 15 VCC POR POR POR CC V VCC RESET Figure 15. MCU RESET VCC
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
Figure 16. MCU RESET
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
RESET ( Table 15) VRST( ) tTOUT MCU
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ATtiny2313/V
Figure 17.
CC
ATtiny2313 BOD(Brown-out Detection) VCC BODLEVEL BOD VBOT+ = VBOT + VHYST/2 VBOT- = VBOT - VHYST/2 Table 16. BODLEVEL (1)
BODLEVEL [1..0] 111 110 101 100 011 010 001 000 Note: 1. VBOT VCC = VBOT VCC ATTINY2313V BODLEVEL = 110 ATtiny2313L BODLEVEL = 101 VBOT VBOT BOD 1.8 2.7 4.3 V VBOT
Table 17.
VHYST tBOD 50 2 mV s
BOD
BOD VCC (VBOT- Figure 18) BOD VCC (VBOT+ Figure 18) tTOUT MCU VCC Table 15 tBOD BOD
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Figure 18.
VCC VBOTVBOT+
RESET
TIME-OUT
tTOUT
INTERNAL RESET
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ATtiny2313/V
1 CK tTOUT Figure 19.
CC
CK
MCU MCUSR
MCU MCU
Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUSR
* Bit 3 - WDRF: "0" * Bit 2 - BORF: "0" * Bit 1 - EXTRF: "0" * Bit 0 - PORF: "0"
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ATtiny2313 Table 18. 1. BOD ( BODLEVEL [2..0] ) 2. (ACSR ACBG ) BOD ACBG Table 18. (1)
VBG tBG IBG Note: 1. VCC = 2.7V, TA = 25C VCC = 2.7V, TA = 25C VCC = 2.7V, TA = 25C 1.0 1.1 40 15 1.2 70 V s A
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ATtiny2313/V
ATtiny2313 (WDT) * * 3
- - - * 16ms 8s *
Figure 20.
128kHz OSCILLATOR
OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K
WATCHDOG RESET WDE
WDP0 WDP1 WDP2 WDP3
MCU RESET
WDIF INTERRUPT
WDIE
128 kHz WDT WDT WDT WDTON (WDE) (WDTIE) 1 0 1. WDCE WDE "1" WDE "1" 2. WDE WDP WDCE
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C WDT ( ) (1)
WDT_off: ; cli ; WDT wdr ; MCUSR WDRF in andi out r16, MCUSR r16, (0xff & (0<; WDCE WDE 1 ; in ori out ldi out sei ret r16, WDTCR r16, (1<; WDT
;
C (1)
void WDT_off(void) { __disable_interrupt(); __watchdog_reset(); /* MCUSR WDRF*/ MCUSR &= ~(1< WDRF WDE C
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ATtiny2313/V
(1)
WDT_Prescaler_Change: ; cli ; wdr ; in ori out ; -ldi out ; -sei ret r16, WDTCR r16, (1<; = 64K (~0.5 s)
;
C (1)
void WDT_Prescaler_Change(void) { __disable_interrupt(); __watchdog_reset(); /* */ WDTCR |= (1< WDP WDP
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WDTCSR
Bit /
7 WDIF R/W 0
6 WDIE R/W 0
5 WDP3 R/W 0
4 WDCE R/W 0
3 WDE R/W X
2 WDP2 R/W 0
1 WDP1 R/W 0
0 WDP0 R/W 0 WDTCSR
* Bit 7 - WDIF: WDTIF "1" SREG I WDTIE * Bit 6 - WDIE: SREG I WDE WDE WDIF WDIE WDIF( ) WDIE Table 19.
WDTON 0 0 0 0 1 WDE 0 0 1 1 x WDIE 0 1 0 1 x
* Bit 4 - WDCE: WDE WDCE WDE / "1" WDCE * Bit 3 - WDE: WDE MCUSR WDRF WDRF WDE WDE WDRF * Bit 5, 2..0 - WDP3..0: 3, 2, 1 0 WDP3..0 P40Table 20 Table 20.
WDP3 0 0 0 WDP2 0 0 0 WDP1 0 0 1 WDP0 0 1 0 2K (2048) 4K (4096) 8K (8192) VCC = 5.0V 16 ms 32 ms 64 ms
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ATtiny2313/V
Table 20.
WDP3 0 0 0 0 0 1 1 1 1 1 1 1 1 WDP2 0 1 1 1 1 0 0 0 0 1 1 1 1 WDP1 1 0 0 1 1 0 0 1 1 0 0 1 1 WDP0 1 0 1 0 1 0 1 0 1 0 1 0 1 16K (16384) 32K (32768) 64K (65536) 128K (131072) 256K (262144) 512K (524288) 1024K (1048576) VCC = 5.0V 0.125 s 0.25 s 0.5 s 1.0 s 2.0 s 4.0 s 8.0 s
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ATtiny2313
ATtiny2313 AVRP11"" Table 21.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 RESET INT0 INT1 TIMER1 CAPT TIMER1 COMPA TIMER1 OVF TIMER0 OVF USART0, RX USART0, UDRE USART0, TX ANALOG COMP PCINT TIMER1 COMPB TIMER0 COMPA TIMER0 COMPB USI START USI OVERFLOW EE READY WDT OVERFLOW 0 1 / 1 / 1 A / 1 / 0 USART0 USART0 USART0 / 1 B / 0 A / 0 B USI USI EEPROM
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ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
ATtiny2313
0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 ; 0x0013 0x0014 0x0015 0x0016 ... ... RESET: ldi out sei ... xxx ... r16, low(RAMEND); SPL,r16
RAM
; ; 0 ; 1 ; 1 ; 1 A ; 1 ; 0 ; USART0 ; USART0,UDR ; USART0 ; ; ; 1 B ; 0 A ; 0 B ; USI ; USI ; EEPROM ;
rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp rjmp
RESET INT0 INT1 TIM1_CAPT TIM1_COMPA TIM1_OVF TIM0_OVF USART0_RXC USART0_DRE USART0_TXC ANA_COMP PCINT TIMER1_COMPB TIMER0_COMPA TIMER0_COMPB USI_START USI_OVERFLOW EE_READY WDT_OVERFLOW
;
43
2543F-AVR-07/04
I/O
I/O AVR I/O - - SBI CBI LED VCC Figure 21 P168" " Figure 21. I/O
Rpu
Pxn
Logic Cpin
See Figure "General Digital I/O" for Details
"x" "n" PORTB3 B 3 PORTxn I/O P56"I/O " I/O - PORTx - DDRx - PINx / PINx "1" "0" "1" MCUCR PUD I/O P44" I/O " P48" " I/O
I/O
I/O Figure 22 I/O
44
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Figure 22. I/O(1)
PUD
Q
D
DDxn Q CLR
RESET
WDx RDx
1 Pxn
Q D PORTxn Q CLR
0
WPx RESET WRx SLEEP RRx
SYNCHRONIZER
D Q D Q
RPx
PINxn L Q Q
clk I/O
PUD: SLEEP: clkI/O:
PULLUP DISABLE SLEEP CONTROL I/O CLOCK
WDx: RDx: WRx: RRx: RPx: WPx:
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER
Note:
1. WRx, WPx, WDx, RRx, RPx RDx clkI/O, SLEEP PUD
DDxn PORTxn PINxn P56"I/O " DDxn DDRx PORTxn PORTx PINxn PINx DDxn DDxn "1" Pxn PORTxn "1" PORTxn PORTxn "1" ("1") ("0")

PINxn "1" PORTxn DDRxn SBI ( ) ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11) ({DDxn, PORTxn} = 0b01) ({DDxn, PORTxn} = 0b10) MCUCR PUD ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b10)
DATA BUS
45
2543F-AVR-07/04
Table 22 Table 22.
PUD ( MCUCR2 ) X 0 1 X X No Yes No No No
DDxn 0 0 0 1 1
PORTxn 0 1 1 0 1
I/O
(Hi-Z) (Hi-Z) ( ) ( )
DDxn PINxn Figure 22 PINxn Figure 23 tpd,max tpd,min Figure 23.
SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd, max t pd, min 0xFF XXX XXX in r17, PINx
46
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
SYNC LATCH PINxn tpd,max tpd,min 1/2 ~ 11/2 Figure 24 out in nop out SYNC LATCH tpd Figure 24.
SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd 0xFF out PORTx, r16 nop 0xFF in r17, PINx
47
2543F-AVR-07/04
B 0 1 2 3 4 7 6 7 nop (1)
... ;
;
ldi ldi out out nop
r16,(1<; nop ; in ... r16,PINB
C
unsigned char i; ... /* */
/* */
PORTB = (1< Figure 22 ( ) SLEEP MCU Standby VCC/2 SLEEP SLEEP SLEEP P48" " ("1") " " "1" "0" "0" "1"
I/O Figure 25 Figure 22 AVR
48
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Figure 25. (1)
PUOExn PUOVxn
1 0
PUD
DDOExn DDOVxn
1 0
Q D DDxn Q CLR
PVOExn PVOVxn
WDx RESET RDx
1 Pxn 0
Q D
1 0
PORTxn
DIEOExn DIEOVxn
1 0
Q CLR
PTOExn WPx
RESET RRx
WRx
SLEEP SYNCHRONIZER
D
SET
RPx
Q
D
Q
PINxn L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn:
Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE
PUD: WDx: RDx: RRx: WRx: RPx: WPx: clkI/O: DIxn: AIOxn:
PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx
Note:
1. WPx, WDx, RLx, RPxRDx I/O, SLEEP clk PUD
Table 23 Figure 25
2543F-AVR-07/04
DATA BUS
49
Table 23.
PUOE PUOV {DDxn, PORTxn, PUD} = 0b010 PUOE PUOV / / DDxnPORTxn PUD DDOV DDxn DDOE DDOV / / DDxn PVOV PVOE PORTxn PVOE PVOV PORTxn PTOE DIEOV DIEOE MCU ( ) DIEOE DIEOV / / MCU ( ) /
PUOV
DDOE DDOV PVOE
PVOV PTOE DIEOE
DIEOV DI
AIO
/

50
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
MCU MCUCR
Bit / 7 PUD R/W 0 6 SM1 R/W 0 5 SE R/W 0 4 SM0 R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR
* Bit 7 - PUD: 1 DDxn PORTxn ({DDxn, PORTxn} = 0b01) I/O P45" " A A Table 5 Table 24. A
PA2 PA1 PA0 RESET, dW XTAL2 XTAL1
B
B Table 25 Table 25. B
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 USCK/SCL/PCINT7 DO/PCINT6 DI/SDA/PCINT5 OC1B/PCINT4 OC1A/PCINT3 OC0A/PCINT2 AIN1/PCINT1 AIN0/PCINT0
* USCK/SCL/PCINT7 - B, Bit 7 USCK SCL USI PCINT7 7 PB7 * DO/PCINT6 - B, Bit 6 DO PORTB6 DDB6 1 PORTB6 1PORTB6 PCINT6 6 PB6 * DI/SDA/PCINT5 - B, Bit 5 DI
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2543F-AVR-07/04
SDA PCINT5 5 PB5 * OC1B/PCINT4 - B, Bit 4 OC1B B PB4 T/C1 B (DDB6 1) OC1B PWM PCINT4 4 PB4 * OC1A/PCINT3 - B, Bit 3 OC1A A PB3 T/C1 A (DDB3 1) OC1A PWM PCINT3 3 PB3 * OC0A/PCINT2 - B, Bit 2 OC0A A PB2 T/C0 A (DDB2 1) OC0A PWM PCINT2 2 PB2 * AIN1/PCINT1 - B, Bit 1 AIN1 PCINT1 1 PB1 * AIN0/PCINT0 - B, Bit 0 AIN0 PCINT0 0 PB0 Table 26Table 27B P49Figure 25 SPI MSTR INPUT SPI SLAVE OUTPUT MISO MOSI SPI MSTR OUTPUT SPI SLAVE INPUT
52
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Table 26. PB7..PB4
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI PB7/USCK/ SCL/PCINT7 0 0 USI_TWO_WIRE (USI_SCL_HOLD + PORTB7)*DDB7 USI_TWO_WIRE * DDRB7 0 USI_PTOE (PCINT7*PCIE) +USISIE 1 PCINT7 USCK SCL - PB6/DO/PCINT6 0 0 0 0 USI_THREE_WIRE DO 0 (PCINT6*PCIE) 1 PCINT6 PB5/SDA/ DI/PCINT5 0 0 USI_TWO_WIRE (SDA + PORTB5)* DDRB5 USI_TWO_WIRE * DDRB5 0 0 (PCINT5*PCIE) + USISIE 1 PCINT5 SDA DI - PB4/OC1B/ PCINT4 0 0 0 0 OC1B_PVOE 0OC1B_PVOV 0 (PCINT4*PCIE) 1 PCINT4
AIO
-
-
Table 27. PB3..PB0
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PB3/OC1A/ PCINT3 0 0 0 0 OC1A_PVOE OC1A_PVOV 0 (PCINT3 * PCIE) 1 PCINT7 - PB2/OC0A/ PCINT2 0 0 0 0 OC0A_PVOE OC0A_PVOV 0 (PCINT2 * PCIE) 1 PCINT6 - PB1/AIN1/ PCINT1 0 0 0 0 0 0 0 (PCINT1 * PCIE) 1 PCINT5 AIN1 PB0/AIN0/ PCINT0 0 0 0 0 0 0 0 (PCINT0 * PCIE) 1 PCINT4 AIN0
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2543F-AVR-07/04
D
D Table 28 Table 28. D
PD6 PD5 PD4 PD3 PD2 PD1 PD0 ICP OC0B/T1 T0 INT1 INT0/XCK/CKOUT TXD RXD
* ICP - D, Bit 6 ICPT/C1 PD6 T/C1 * OC1B/T1 - D, Bit 5 OC0B B PD5 T/C0 B (DDB5 1) OC0B PWM T1 T/C1 TCCR1 CS02 CS01 T/C1 * T0 - D, Bit 4 T0 T/C0 TCCR0 CS02 CS01 T/C0 * INT1 - D, Bit 3 INT0 0 PD3 MCU * INT0/XCK/CKOUT - D, Bit 2 INT1 1 PD2 MCU XCK USART CKOUT * TXD - D, Bit 1 TXD UART * RXD - D, Bit 0 RXD UART
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ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Table 29 Table 30 D P49Figure 25 Table 29. PD7..PD4
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PD6/ICP 0 0 0 0 0 0 0 ICP 1 ICP - PD5/OC1B/T1 0 0 0 0 OC1B_PVOE OC1B_PVOV 0 T1 1 T1 - PD4/T0 0 0 0 0 0 0 0 T0 1 T0 AIN1
Table 30. PD3..PD0
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PD3/INT1 0 0 0 0 0 0 0 INT1 1 INT1 - PD2/INT0/XCK/ CKOUT 0 0 0 0 XCKO_PVOE XCKO_PVOV 0 INT0 / XCK 1 INT0 / XCK - PD1/TXD TXD_OE 0 TXD_OE 1 TXD_OE TXD_PVOV 0 0 0 - - PD0/RXD RXD_OE PORTD0 * PUD RXD_EN 0 0 0 0 0 0 RXD -
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2543F-AVR-07/04
I/O
A PORTA
Bit / 7
-
6
-
5
-
4
-
3
-
2
PORTA2
1
PORTA1
0
PORTA0
PORTA
R 0
R 0
R 0
R 0
R 0
R/W 0
R/W 0
R/W 0
A DDRA
Bit /
7
-
6
-
5
-
4
-
3
-
2 DDA2 R/W 0
1 DDA1 R/W 0
0 DDA0 R/W 0 DDRA
R 0
R 0
R 0
R 0
R 0
A PINA
Bit /
7
-
6
-
5
-
4
-
3
-
2 PINA2 R/W N/A
1 PINA1 R/W N/A
0 PINA0 R/W N/A PINA
R N/A
R N/A
R N/A
R N/A
R N/A
B PORTB
Bit /
7
PORTB7
6
PORTB6
5
PORTB5
4
PORTB4
3
PORTB3
2
PORTB2
1
PORTB1
0
PORTB0 PORTB
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
B DDRB
Bit /
7 DDB7 R/W 0
6 DDB6 R/W 0
5 DDB5 R/W 0
4 DDB4 R/W 0
3 DDB3 R/W 0
2 DDB2 R/W 0
1 DDB1 R/W 0
0 DDB0 R/W 0 DDRB
B PINB
Bit /
7 PINB7 R/W N/A
6 PINB6 R/W N/A
5 PINB5 R/W N/A
4 PINB4 R/W N/A
3 PINB3 R/W N/A
2 PINB2 R/W N/A
1 PINB1 R/W N/A
0 PINB0 R/W N/A PINB
D PORTD
Bit /
7
-
6
PORTD6
5
PORTD5
4
PORTD4
3
PORTD3
2
PORTD2
1
PORTD1
0
PORTD0 PORTD
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
D DDRD
Bit /
7 - R 0
6 DDD6 R/W 0
5 DDD5 R/W 0
4 DDD4 R/W 0
3 DDD3 R/W 0
2 DDD2 R/W 0
1 DDD1 R/W 0
0 DDD0 R/W 0 DDRD
D PIND
Bit /
7 - R N/A
6 PIND6 R/W N/A
5 PIND5 R/W N/A
4 PIND4 R/W N/A
3 PIND3 R/W N/A
2 PIND2 R/W N/A
1 PIND1 R/W N/A
0 PIND0 R/W N/A PIND
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ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
INT0 INT1 PCINT7..0 INT0 INT1 PCINT7..0 PCINT7..0 PCI0 PCMSK1 PCMSK0 PCINT7..0 A - EICRA INT0 INT1 P21" " I/O INT0 INT1 ( ) I/O MCU MCU P21" " SUT CKSEL MCU MCUCR A
Bit / 7 PUD R/W 0 6 SM1 R/W 0 5 SE R/W 0 4 SMD R/W 0 3 ISC11 R/W 0 2 ISC10 R/W 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR
* Bit 3, 2 - ISC11, ISC10: 1 Bit 1 Bit 0 SREG I 1 INT1 Table 32 MCU INT1 Table 31. 1
ISC11 0 0 1 1 ISC10 0 1 0 1 INT1 INT1 INT1 INT1
* Bit 1, 0 - ISC01, ISC00: 0 Bit1 Bit 0 SREG I 0 INT0 Table 32 MCU INT0 Table 32. 0
ISC01 0 0 1 1 ISC00 0 1 0 1 INT0 INT0 INT0 INT0
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2543F-AVR-07/04
GIMSK
Bit /
7 INT1 R/W 0
6 INT0 R/W 0
5 PCIE R/W 0
4 - R 0
3 - R 0
2 - R 0
1 - R 0
0 - R 0 GIMSK
* Bit 7 - INT1: 1 INT1 '1' SREG I 1 1/0 (ISC11 ISC10) INT1 INT1 * Bit 6 - INT0: 0 INT0 '1' SREG I 0 1/0 (ISC01 ISC00) INT0 INT0 * Bit 5 - PCIE: PCIE '1' SREG I PCINT7..0 PCI PCINT7..0 PCMSK
58
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
EIFR
Bit / 7 INTF1 R/W 0 6 INTF0 R/W 0 5 PCIF R/W 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 EIFR
* Bit 7 - INTF1: 1 INT1 INTF1 SREG I GIMSK INT1 "1" MCU "1" INT1 * Bit 6 - INTF0: 0 INT0 INTF0 SREG I GIMSK INT0 "1" MCU "1" INT0 * Bit 5 - PCIF: PCINT7..0 PCIF "1" SREG I GIMSK PCIE "1"MCU "1" PCMSK
Bit / 7
PCINT7
6
PCINT6
5
PCINT5
4
PCINT4
3
PCINT3
2
PCINT2
1
PCINT1
0
PCINT0 PCMSK
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 7..0 - PCINT7..0: 15..8 PCINT7..0 I/O PCINT7..0 PCIE PCINT7..0
59
2543F-AVR-07/04
PWM 8 / 0
T/C0 8 / PWM * * * ( ) * PWM * PWM * * (TOV0, OCF0A OCF0B) Figure 268/ P2"ATtiny2313 " CPU I/O I/O P69"8 / " Figure 26. 8 T/C
Count Clear Direction Control Logic TOVn (Int.Req.) clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn
=
=0
OCnA (Int.Req.)
=
OCRnA Fixed TOP Value
Waveform Generation
OCnA
DATA BUS
OCnB (Int.Req.) Waveform Generation OCnB
=
OCRnB
TCCRnA
TCCRnB
T/C(TCNT0)(OCR0A OCR0B) 8 ( Int.Req. ) TIFR0 TIMSK TIFR TIMSK T/C T0 ( )T/C T/C clkT0 (OCR0A OCR0B) T/C PWM OC0 P62 " " (OCF0A OCF0B)
"n" T/C 0 "x" A B TCNT0 T/C0
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ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Table 33 Table 33. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOPTOP 0xFF (MAX) OCR0A
T/C
T/C T/C TCCR0B CS02:0 P75"T/C0 T/C1 " 8 T/C Figure 27 Figure 27.
DATA BUS
TOVn (Int.Req.)
Clock Select count TCNTn clear direction ( From Prescaler ) bottom top Control Logic clkTn Edge Detector Tn
( ) count direction clear clkTn top bottom TCNT0 1 1 TCNT0 ( ) T/C clkT0 TCNT0 TCNT0 (0)
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2543F-AVR-07/04
clkT0 clkT0 CS02:0 (CS02:0 = 0) clkT0 CPU TCNT0 CPU ( ) T/C (TCCR0A) WGM01 WGM00 (TCCR0B) WGM02 OC0A P87" " T/CTOV0WGM01:0 TOV0CPU
8TCNT0OCR0A(OCR0B) TCNT0 OCR0A OCR0B OCF0A( OCF0B) CPU OCF0A( OCF0B) "1" WGM2:0 COM0x1:0 max bottom ( P87" " ) Figure 28 Figure 28.
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top bottom FOCn
Waveform Generator
OCnx
WGMn1:0
COMnX1:0
62
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
PWM OCR0x OCR0x top bottom PWM OCR0x CPU OCR0x CPU OCR0x PWM FOC0x "1" OCF0x / OC0x (COM01:0 OC0x "0"-"1" ) CPU TCNT0 OCR0x TCNT0 TCNT0 TCNT0 T/C TCNT0 OCR0x TCNT0 BOTTOM OC0x OC0x FOC0x OC0x COM0x1:0 COM0x1:0
TCNT0
COM0x1:0 COM0x1:0 (OC0x) COM0x1:0 OC0x Figure 29 COM0x1:0 I/O I/O I/O COM0x1:0 I/O (DDR PORT) OC0xOC0x OC0x OC0x Figure 29.
COMnx1 COMnx0 FOCn
Waveform Generator
D
Q
1 OCn Pin
OCnx D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
63
2543F-AVR-07/04
COM0x1:0 I/O OC0x DDR OC0x DDR_OC0x OC0x COM0x1:0 P69 "8 / " COM0x1:0 CTC PWM COM0x1:0 = 0 OC0x PWM P62Figure 28PWM P53Table 26 PWM P53Table 27 COM0x1:0 PWM FOC0x
- T/C - (WGM02:0) (COM0x1:0) COM0x1:0 PWM PWM COM0x1:0 (P63 " " ) P67"T/C " Figure 33 Figure 34 Figure 35 Figure 36
(WGM02:0 = 0) 8 (TOP = 0xFF) 0x00 TCNT0 T/C TOV0 TOV0 9 TOV0 CPU
CTC( )
CTC (WGM02:0 = 2) OCR0A TCNT0 OCR0A OCR0A TOP CTCFigure 30 TCNT0TCNT0OCR0A TCNT0 Figure 30. CTC
OCnx Interrupt Flag Set
TCNTn
OCn (Toggle) Period
1 2 3 4
(COMnx1:0 = 1)
64
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
OCF0A TOP TOP CTC TOP BOTTOM OCR0A TCNT0 0xFF 0x00 OCF0A CTC OC0A COM0A1:0 = 1 OC0A fOC0 = fclk_I/O/2 (OCR0 A= 0x00) f clk_I/O f OCnx = --------------------------------------------------2 N ( 1 + OCRnx ) N (1 8 64 256 1024) TOV0 MAX 0x00 PWM PWM (WGM02:0 = 3 7) PWM PWM PWM BOTTOM TOP BOTTOM WGM2:0 = 3 TOP 0xFF WGM2:0 = 7 TOPOCR0A OC0xTCNT0OCR0x BOTTOM OC0x PWM PWM PWM DAC ( ) PWM TOP Figure 29 TCNT0 PWM PWM TCNT0 OCR0x TCNT0 Figure 31. PWM
OCRnx Interrupt Flag Set
OCRnx Update and TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
TOP T/C TOV0 PWM OC0x PWM COM0x1:0 2 PWM 3 PWM WGM02
65
2543F-AVR-07/04
COM0A1:0 "1" AC0A OC0B ( P53Table 26) OC0x PWM OC0x OCR0x TCNT0 ( ) ( TOP BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = -----------------N 256 N (1 8 64 256 1024) OCR0A PWM OCR0A BOTTOM MAX+1OCR0AMAX COM0A1:0 OC0x(COM0x1:0 = 1) 50% OCR0A 0 foc0 = fclk_I/O/2 CTC OC0A PWM PWM PWM (WGM02:0 = 1 5) PWM BOTTOM TOP TOP BOTTOM WGM2:0 = 1 TOP 0xFF WGM2:0 = 5 TOP OCR0A TOP TCNT0 OCR0x OC0x BOTTOM TCNT0 OCR0x OC0x TOP TCNT0 TOP Figure 32 TCNT0 PWM PWM TCNT0 OCR0x TCNT0 Figure 32. PWM
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
66
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
BOTTOM T/C TOV0 PWM OC0x PWM COM0x1:0 2 PWM COM0x1:0 3 PWM WGM02 COM0A0 "1" OC0A OC0B ( P53Table 27) OC0x OCR0x TCNT0 OC0x PWM PWM f clk_I/O f OCnxPCPWM = -----------------N 510 N (1 8 64 256 1024) OCR0A PWM PWM OCR0A BOTTOM OCR0A MAX PWM Figure 32 2 OCn BOTTOM * Figure 32 OCR0A MAX OCR0A MAX OCn BOTTOM T/C MAX OCn OCR0A OCn
*
T/C
T/C clkT0 Figure 33 T/C PWM MAX Figure 33. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 33
67
2543F-AVR-07/04
Figure 34. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 35 OCF0B ( CTC )OCF0A OCR0A TOP Figure 35. T/C OCF0x fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 36 CTC PWM OCF0A TCNT0 OCR0A TOP Figure 36. T/C CTC fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRnx
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
68
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
8 /
T/C A TCCR0A
Bit / 7
COM0A1
6
COM0A0
5
COM0B1
4
COM0B0
3
-
2
-
1
WGM01
0
WGM00 TCCR0A
R/W 0
R/W 0
R/W 0
R/W 0
R 0
R 0
R/W 0
R/W 0
* Bits 7:6 - COM0A1:0: A (OC0A) COM0A1:0 OC0A I/O OC0A DDR OC0A COM0A1:0 WGM02:0 Table 34 WGM02:0 CTC ( PWM) COM0A1:0 Table 34. PWM
COM0A1 0 0 1 1 COM0A0 0 1 0 1 OC0A OC0A OC0A OC0A
Table 35 WGM01:0 PWM COM01:0 Table 35. PWM (1)
COM0A1 0 0 1 1 Note: COM0A0 0 1 0 1 OC0A WGM02 = 0: OC0A WGM02 = 1: OC0A OC0A TOP OC0A OC0A TOP OC0A
1. OCR0A TOP COM01 TOP OC0 P65" PWM "
Table 36 WGM02:0 PWM COM0A1:0 Table 36. PWM (1)
COM0A1 0 0 1 1 Note: COM0A0 0 1 0 1 OC0A WGM02 = 0: OC0A WGM02 = 1: OC0A OC0A OC0A OC0A OC0A
1. OCR0A TOP COM0A1 TOP OC0A P66" PWM "
69
2543F-AVR-07/04
* Bits 5:4 - COM0B1:0: B OC0B COM0B1:0 OC0B 1 OC0B COM0B1:0 WGM01:0 Table 37 WGM02:0 CTC COM0B1:0 Table 37. PWM
COM0B1 0 0 1 1 COM0B0 0 1 0 1 OC0B OC0B OC0B OC0B
Table 38 WGM02:0 PWM COM0B1:0 Table 38. PWM (1)
COM0B1 0 0 1 1 Note: COM0B0 0 1 0 1 OC0B OC0B TOP OC0B OC0B TOP OC0B
1. OCR0B TOP COM0B1 TOP OC0B P65" PWM "
Table 39 WGM02:0 PWM COM0B1:0 Table 39. PWM (1)
COM0B1 0 0 1 1 Note: COM0B0 0 1 0 1 OC0B OC0B OC0B OC0B OC0B
1. OCR0B TOP COM0B1 TOP OC0B P66" PWM "
* Bits 3, 2 - Res: * Bits 1:0 - WGM01:0: TCCR0B WGM02 TOP Table 40 T/C ( ) CTC PWM ( P87" " )
70
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Table 40.
Mode 0 1 2 3 4 5 6 7 Notes: WGM2 0 0 0 0 1 1 1 1 WGM1 0 0 1 1 0 0 1 1 WGM0 0 1 0 1 0 1 0 1 T/C PWM CTC PWM PWM PWM TOP 0xFF 0xFF OCRA 0xFF - OCRA - OCRA OCRx TOP TOP - TOP - TOP TOV (1)(2) MAX BOTTOM MAX MAX - BOTTOM - TOP
1. MAX = 0xFF 2. BOTTOM = 0x00
71
2543F-AVR-07/04
T/C B TCCR0B
Bit /
7
FOC0A
6
FOC0B
5
-
4
-
3
WGM02
2
CS02
1
CS01
0
CS00 TCCR0B
W 0
W 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 7 - FOC0A: A FOC0A WGM PWM PWM TCCR0B 1 OC0A COM0A1:0 FOC0A COM0A1:0 FOC0A OCR0ATOPCTC FOC0A 0 * Bit 6 - FOC0B: B FOC0B WGM PWM PWM TCCR0B 1 OC0B COM0B1:0 FOC0B COM0B1:0 FOC0B OCR0BTOPCTC FOC0B 0 * Bits 5:4 - Res: * Bit 3 - WGM02: P69"T/C A TCCR0A" * Bits 2:0 - CS02:0: T/C P73Table 41
72
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Table 41.
CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 T/C clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T0 T0
T/C0 T0 T/C TCNT0
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TCNT0 R/W 0
TCNT0[7:0]
T/C 8 TCNT0 TCNT0 TCNT0 OCR0x A OCR0A
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR0A R/W 0
OCR0A[7:0]
8 TCNT0 OC0A B OCR0B
Bit / 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR0B R/W 0
OCR0B[7:0]
8 TCNT0 OC0B
73
2543F-AVR-07/04
T/C TIMSK
Bit /
7 TOIE1 R/W 0
6 OCIE1A R/W 0
5 OCIE1B R/W 0
4 - R 0
3 ICIE1 R/W 0
2 OCIE0B R/W 0
1 TOIE0 R/W 0
0 OCIE0A R/W 0 TIMSK
* Bit 4 - Res: * Bit 2 - OCIE0B: T/C0 B OCIE0B I "1" T/C B T/C TIFR OCF0B * Bit 1 - TOIE0: T/C0 TOIE0 I "1" T/C0 T/C0 TIFR TOV0 * Bit 0 - OCIE0A: T/C0 A OCIE0A I "1" T/C0 A T/C0 TIFR OCF0A T/C TIFR
Bit / 7 TOV1 R/W 0 6 OCF1A R/W 0 5 OCF1B R/W 0 4 - R 0 3 ICF1 R/W 0 2 OCF0B R/W 0 1 TOV0 R/W 0 0 OCF0A R/W 0 TIFR
* Bit 4 - Res: * Bit 2 - OCF0B: 0 B T/C OCR0B( 0B) OCF0B 1 SREG I OCIE0B(T/C0 B ) OCF0B * Bit 1 - TOV0: T/C0 T/C0 TOV0 TOV0 1 SREG I TOIE0(T/C0 ) TOV0 WGM02:0 Table 40 P71" " * Bit 0 - OCF0A: 0 A T/C0 OCR0A( 0) OCF0A 1 SREG I OCIE0A(T/C0 ) OCF0A
74
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
T/C0 T/C1
T/C1 T/C0 T/C1 T/C0 CSn2:0 = 1 T/C T/C fCLK_I/O 4 fCLK_I/O/8 fCLK_I/O/64 fCLK_I/O/256 fCLK_I/O/1024 T/C T/C1 T/C0 T/C (6 > CSn2:0 > 1) 1 N+1 N (8 64 256 1024) T/C T/C T/C T1/T0 T/C clkT1/clkT0 T1/T0 ( ) Figure 37 T1/T0 clkI/O CSn2:0 = 7 clkT1 CSn2:0 = 6 clkT1/clkT0 Figure 37. T1/T0
Tn_sync (To Clock Select Logic)
Tn
D LE
Q
D
Q
D
Q
clk I/O
Synchronization Edge Detector
T1/T0 2.5 3.5 T1/T0 T/C 50% (fExtClk < fclk_I/O/2) (Nyquist ) ( ) fclk_I/O/2.5
75
2543F-AVR-07/04
Figure 38. T/C0 T/C1 (1)
clk I/O
Clear
PSR10
T0
Synchronization
T1
Synchronization
clkT1
clkT0
Note:
1. (T1/T0) Figure 37.
T/C GTCCR
Bit /
7 -- R 0
6 - R 0
5 - R 0
4 - R 0
3 - R 0
2 - R 0
1 -- R 0
0 PSR10 R/W 0 GTCCR
* Bits 7..1 - Res: * Bit 0 - PSR10: T/C1 T/C0 T/C1 T/C0 T/C1 T/C0
76
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
16 / 1
16T/C() * 16 ( 16 PWM) * 2 * * * * ( ) * PWM * PWM * * * 4 (TOV1OCF1A OCF1B ICF1) "n" T/C "x" TCNT1 T/C1 16 T/C Figure 39 P2"ATtiny2313 I/O " CPUI/O I/OI/O I/O P97"16 / " Figure 39. 16 T/C (1)
Count Clear Direction Control Logic TOVn (Int.Req.) clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn
=
=0
OCnA (Int.Req.)
=
OCRnA Fixed TOP Values
Waveform Generation
OCnA
DATA BUS
OCnB (Int.Req.) Waveform Generation OCnB
=
OCRnB ICFn (Int.Req.) Edge Detector
( From Analog Comparator Ouput )
ICRn
Noise Canceler ICPn
TCCRnA
TCCRnB
Note:
1. P2Figure 1 P56Table 25 P61Table 31 T/C1
/ TCNT1 OCR1A/B ICR1 16 16 P78" 16 " T/C TCCR1A/B 8 CPU (
77
2543F-AVR-07/04
Int.Req.) TIFR1 TIMSK TIFR TIMSK T/CT1 T/C( ) T/C clkT1 OCR1A/B T/C PWM OC1A/B P84 " " OCF1A/B ICP1 ( P141 " " ) ( ) T/C ( ) TOP T/C OCR1A ICR1 PWM OCR1A TOP OCR1A PWM OCR1A TOP TOP ICR1 OCR1A PWM Table 42.
BOTTOM MAX TOP 0x0000 BOTTOM 0xFFFF ( 65535) MAX TOP TOP 0x00FF 0x01FF 0x03FF OCR1A ICR1
16T/C16AVRT/C * * * * * * * * 16 T/C I/O 16 T/C PWM10 WGM10 PWM11 WGM11 CTC1 WGM12 TCCR1C FOC1A FOC1B TCCR1B WGM13
16 T/C
16 T/C
16
TCNT1 OCR1A/B ICR1 AVR CPU 8 16 16 1688 16 16 16 CPU 16 8 8 16 16 CPU 16
78
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
16 OCR1A/B 16 16 16 OCR1A/B ICR1 "C" 16
(1)
... ; TCNT1 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; TCNT1 r17:r16 in in ... r16,TCNT1L r17,TCNT1H
C (1)
unsigned int i; ... /* TCNT1 0x01FF */ TCNT1 = 0x1FF; /* TCNT1 i */ i = TCNT1; ...
Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
r17:r16 TCNT1 16 16 16 16 16
79
2543F-AVR-07/04
TCNT1 OCR1A/B ICR1 (1)
TIM16_ReadTCNT1: ; in cli ; TCNT1 r17:r16 in in r16,TCNT1L r17,TCNT1H r18,SREG ;
; out SREG,r18 ret
C (1)
unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ i = TCNT1; /* */ SREG = sreg; return i; }
Note:
1. I/O I/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
TCNT1 r17:r16
80
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
TCNT1 OCR1A/B ICR1 (1)
TIM16_WriteTCNT1: ; in cli ; TCNT1 r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; out SREG,r18 ret r18,SREG ;
C (1)
void TIM16_WriteTCNT1 ( unsigned int i ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ TCNT1 = i; /* */ SREG = sreg; }
Note:
1. I/O I/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
r17:r16 TCNT1 16
81
2543F-AVR-07/04
/
T/C T/C B(TCCR1B) (CS12:0) P75"T/C0 T/C1 " 16 T/C 16 Figure 40 Figure 40.
DATA BUS
(8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) Clear Direction Control Logic clkTn Edge Detector Tn
TCNTn (16-bit Counter)
( From Prescaler ) TOP BOTTOM
( ) Count Direction Clear clkT1 TOP BOTTOM TCNT1 1 1 TCNT1 / TCNT1 TCNT1 (0)
16 8 I/O TCNT1H 8 TCNT1L 8 CPU TCNT1H CPU TCNT1H (TEMP) TCNT1L TCNT1HTCNT1L TCNT1H CPU 8 16 TCNT1 clkT1 1 1 clkT1 CS12:0 CS12:0= 0 CPU TCNT1 clkT1 CPU TCCR1A TCCR1B WGM13:0 ( ) OC1x P87" " WGM13:0 TOV1 TOV1 CPU
T/C ICP1 Figure 41 "n" /
82
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Figure 41.
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit) WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
ICRn (16-bit Register)
TCNTn (16-bit Counter)
ACO* Analog Comparator ICPn
ACIC*
ICNC
ICES
Noise Canceler
Edge Detector
ICFn (Int.Req.)
ICP1 ( ) ACO 16 TCNT1 ICR1 ICF1 ICIE1 = 1 ICF1 I/O "1" ICR1 ICR1L ICR1H TEMP CPU ICR1H TEMP ICR1 ICR1 TOP ICR1 WGM13:0 ICR1 ICR1H I/O ICR1L P78" 16 " 16 ICP1T/C1 ACSR ACIC ICP1ACOT1(P75Figure 37), 4 ICR1 TOP T/C ICP1 4 4 TCCR1B ICNC1 ICR1 4
83
2543F-AVR-07/04
ICR1 ICR1 ICR1 TOP ICR1 ICF1 ( I/O "1") ICF1
16 TCNT1 OCR1x OCF1x OCIE1x = 1 OCF1x OCF1x I/O "1" WGM13:0 COM1x1:0 TOP BOTTOM (P87 " " ) A T/C TOP ( ) TOP Figure 42 "n" (n = 1 T/C1) "x" (A/B) Figure 42.
DATA BUS
(8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit)
OCRnxL Buf. (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
OCRnx Buffer (16-bit Register)
TCNTn (16-bit Counter)
OCRnxH (8-bit)
OCRnxL (8-bit)
OCRnx (16-bit Register)
= (16-bit Comparator )
OCFnx (Int.Req.) TOP BOTTOM
Waveform Generator
OCnx
WGMn3:0
COMnx1:0
T/C 12 PWM OCR1x (CTC) OCR1x TOP BOTTOM PWM OCR1x CPU OCR1x CPU OCR1x OCR1x( ) (T/C TCNT1 ICR1 84
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
) OCR1x TEMP 16 OCR1x TEMP OCR1xH CPU I/O TEMP OCR1xL TEMP OCR1x OCR1x P78" 16 " 16 PWM FOC1x "1" OCF1x / OC1x (COMx1:0 OC1x ) CPUTCNT1 OCR1x TCNT1 TCNT1 TCNT1 T/C TCNT1OCR1x PWM TOP TCNT1 TOP 0xFFFF TCNT1BOTTOM OC1x OC1x FOC1x OC1x COM1x1:0 COM1x1:0
TCNT1
85
2543F-AVR-07/04
COM1x1:0 COM1x1:0 OC1x COM1x1:0 OC1x Figure 43 COM1x1:0 I/O I/O I/O COM1x1:0 I/O (DDR PORT) OC1x OC1x OC1x COM1x "0" Figure 43.
COMnx1 COMnx0 FOCnx
Waveform Generator
D
Q
1 OCnx Pin
OCnx D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
COM1x1:0 OC1x I/O OC1x (DDR) OC1x DDR_OC1x Table 43Table 44 Table 45 OC1x COM1x1:0 P97 "16 / " COM1x1:0
86
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
COM1x1:0 CTC PWM COM1x1:0 = 0 OC1x PWM P97Table 43 PWM P97Table 44 PWM P98Table 45 COM1x1:0 PWM FOC1x
- T/C - (WGM13:0) (COM1x1:0) COM1x1:0 PWM PWM COM1x1:0 (P86 " " ) P95" / "
(WGM13:0 = 0) (MAX = 0xFFFF) 0x0000 TCNT1T/CTOV1 TOV117 TOV1 CPU
CTC( )
CTC (WGM13:0 = 4 12) OCR1A ICR1 TCNT1 OCR1A(WGM13:0 = 4) ICR1 (WGM13:0 = 12) OCR1A ICR1 TOP CTC P87Figure 44 TCNT1 TCNT1 OCR1A ICR1 TCNT1 Figure 44. CTC
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnA (Toggle) Period
1 2 3 4
(COMnA1:0 = 1)
OCF1A ICF1 TOP TOP CTC TOP BOTTOM OCR1A ICR1 TCNT1 87
2543F-AVR-07/04
0xFFFF 0x0000 OCR1A ICR1 PWM OCR1A TOP (WGM13:0 = 15) OCR1A CTC OC1A COM1A1:0 = 1 OC1A (DDR_OC1A = 1) fOC2 = fclk_I/O/2 (OCR1A = 0x0000) f clk_I/O f OCnA = ---------------------------------------------------2 N ( 1 + OCRnA ) N (1 8 64 256 1024) TOV1 MAX 0x0000
88
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
PWM PWM (WGM13:0 = 5 6 7 14 15) PWM PWM PWM BOTTOM TOP BOTTOM OC1x TCNT1 OCR1x TOP OCR1x PWM PWM PWM DAC ( ) PWM PWM 89 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R FPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 5 6 7)ICR1 (WGM13:0 = 14) OCR1A (WGM13:0 = 15) Figure 45 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 45. PWM
OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
8
TOP T/C TOV1 TOP OCR1A ICR1 OC1A ICF1 TOV1 TOP TOPTOP TCNT1OCR1x TOP OCR1x "0" TOP ICR1 OCR1A ICR1 ICR1 ICR1 TCNT1 0xFFFF 0x0000 OCR1A OCR1A OCR1A TCNT1 TOP OCR1A TCNT1 TOV1
89
2543F-AVR-07/04
TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A PWM OC1x PWM COM1x1:0 2 PWM 3 PWM ( P97Table 43) OC1x DDR_OC1x PWM OC1x OCR1x TCNT1 ( ) ( TOP BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = ----------------------------------N ( 1 + TOP ) N (1 8 64 256 1024) OCR1x PWM OCR1x BOTTOM(0x0000) TOP+1OCR1xTOP COM1x1:0 OC1A (COM1A1:0 = 1) 50% OCR1A TOP (WGM13:0 = 15) OCR1A 0(0x0000) foc2 = fclk_I/O/2 CTC OC1A PWM
90
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
PWM PWM (WGM13:0 = 1 2 3 11) 10 PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x OC1x BOTTOM TCNT1 OCR1x OC1x PWM PWM 8 9 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 12 3) ICR1 (WGM13:0 = 10) OCR1A (WGM13:0 = 11) TCNT1 TOP Figure 46 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 46. PWM
OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
BOTTOM T/C TOV1 TOP OCR1A ICR1 OCR1x OC1A ICF1 TOPTOP TCNT1OCR1x TOP OCR1x "0" Figure 46 T/C TOP OCR1x OCR1x / TOP PWM TOP TOP
91
2543F-AVR-07/04
T/C TOP TOP PWM OC1x PWM COM1x1:0 2 PWM COM1x1:0 3 PWM ( P97Table 44) OC1xDDR_OC1x OCR1x TCNT1 OC1x PWM PWM f clk_I/O f OCnxPCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM
92
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
PWM PWM (WGM13:0 = 8 9) - PWM - PWM PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x OC1xBOTTOMTCNT1OCR1x OC1x PWM PWM OCR1x Figure 46 Figure 47 PWM PWM ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) PWM ICR1 (WGM13:0 = 8) OCR1A (WGM13:0 = 9) TCNT1 TOP Figure 47 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 47. PWM
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
OCR1x T/C TOV1 TOP OCR1A ICR1 TCNT1 TOP OC1A ICF1 TOP BOTTOM TOPTOP TCNT1OCR1x Figure 47 PWM OCR1x BOTTOM
93
2543F-AVR-07/04
TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A PWM OC1x PWM COM1x1:0 2 PWM 3 PWM ( P98Table 45) OC1x PWM OC1x OCR1x TCNT1 ( ) TCNT1 ( ) PWM f clk_I/O f OCnxPFCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM
94
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
/
/ clkT1 OCR1x OCR1x ( ) Figure 48 OCF1x Figure 48. T/C OCF1x
clkI/O clkTn
(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 49 Figure 49. T/C OCF1x fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 50 TOP PWM OCR1x BOTTOM TOP BOTTOM BOTTOM+1 TOP-1 BOTTOM TOV1
95
2543F-AVR-07/04
Figure 50. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
Figure 51 Figure 51. T/C fclk_I/O/8
clk I/O clk Tn
(clk /8) I/O
TCNTn
(CTC and FPWM)
TOP - 1 TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICF n (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
96
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
16 /
T/C1 A TCCR1A
Bit / 7
COM1A1
6
COM1A0
5
COM1B1
4
COM1B0
3
-
2
-
1
WGM11
0
WGM10 TCCR1A
R/W 0
R/W 0
R/W 0
R/W 0
R 0
R 0
R/W 0
R/W 0
* Bit 7:6 - COM1A1:0: A * Bit 5:4 - COM1B1:0: B COM1A1:0 COM1B1:0 OC1A OC1B COM1A1:0 "1"OC1A I/O COM1B1:0 "1" OC1BI/O OC1AOC1B OC1A( OC1B) COM1x1:0 WGM13:0 Table 43 WGM13:0 CTC ( PWM) COM1x1:0 Table 43. PWM
COM1A1/COM1B1 0 0 1 1 COM1A0/COM1B0 0 1 0 1 OC1A/OC1B OC1A/OC1B OC1A/OC1B( ) OC1A/OC1B( )
Table 44 WGM13:0 PWM COM1x1:0 Table 44. PWM(1)
COM1A1/COM1B1 0 0 COM1A0/COM1B0 0 1 OC1A/OC1B WGM13=0: OC1A/OC1B WGM13=1: OC1A OC1B OC1A/OC1B TOP OC1A/OC1B OC1A/OC1B TOP OC1A/OC1B
1 1 Note:
0 1
1. OCR1A/OCR1B TOP COM1A1/COM1B1 OC1A/OC1B / P89 " PWM "
97
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Table 45WGM13:0PWMPWMCOM1x1:0 Table 45. PWM (1)
COM1A1/COM1B1 0 0 COM1A0/COM1B0 0 1 OC1A/OC1B WGM13=0: OC1A/OC1B WGM13=1: OC1A OC1B/OCnC OC1A/OC1B OC1A/OC1B OC1A/OC1B OC1A/OC1B
1 1 Note:
0 1
1. OCR1A/OCR1B TOP COM1A1/COM1B1 P91 " PWM "
* Bit 1:0 - WGM11:0: TCCR1B WGM13:2 ---- Table 46 T/C ( ) (CTC) (PWM) (P87 " " )
98
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ATtiny2313/V
Table 46. (1)
Mode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: WGM13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WGM12 (CTC1) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WGM11 (PWM11) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WGM10 (PWM10) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 / 8 PWM 9 PWM 10 PWM CTC 8 PWM 9 PWM 10 PWM PWM PWM PWM PWM CTC PWM PWM TOP 0xFFFF 0x00FF 0x01FF 0x03FF OCR1A 0x00FF 0x01FF 0x03FF ICR1 OCR1A ICR1 OCR1A ICR1 - ICR1 OCR1A OCR1x TOP TOP TOP TOP TOP TOP BOTTOM BOTTOM TOP TOP - TOP TOP TOV1 MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP TOP BOTTOM BOTTOM BOTTOM BOTTOM MAX - TOP TOP
1. CTC1 PWM11:0 WGM12:0
99
2543F-AVR-07/04
T/C1 B TCCR1B
Bit /
7 ICNC1 R/W 0
6 ICES1 R/W 0
5 - R 0
4 WGM13 R/W 0
3 WGM12 R/W 0
2 CS12 R/W 0
1 CS11 R/W 0
0 CS10 R/W 0 TCCR1B
* Bit 7 - ICNC1: ICNC1 ICP1 ICP1 4 4 4 * Bit 6 - ICES1: ICP1 ICES1 "0" ICES1 "1" ICES1 ICR1 ICF1 ICR1 TOP ( TCCR1A TCCR1B WGM13:0 ) ICP1 * Bit 5 - TCCR1B "0" * Bit 4:3 - WGM13:2: TCCR1A * Bit 2:0 - CS12:0: 3 T/C Figure 48 Figure 49 Table 47.
CS12 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 (T/C ) clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T1 T1
T1 1 T/C1 T/C1 C TCCR1C
Bit / 7 FOC1A W 0 6 FOC1B W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 TCCR1C
* Bit 7 - FOC1A: A * Bit 6 - FOC1B: B
100
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FOC1A/FOC1BWGM13:0PWM PWM TCCR1A 1 FOC1A/FOC1B "1" COM1x1:0 OC1A/OC1B FOC1A/FOC1B COM1x1:0 FOC1A/FOC1B OCR1A TOP CTC FOC1A/FOC1B T/C1 TCNT1H TCNT1L
Bit 7 6 5 4 3 2 1 0 TCNT1H TCNT1L R/W 0 R/W 0 R/W 0
TCNT1[15:8] TCNT1[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
TCNT1HTCNT1LT/C1TCNT1 / 16 CPU 8 TEMPTEMP 16 P78 " 16 " TCNT1TCNT1OCR1x TCNT1 1A OCR1AH OCR1AL
Bit 7 6 5 4 3 2 1 0 OCR1AH OCR1AL R/W 0 R/W 0 R/W 0
OCR1A[15:8] OCR1A[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
101
2543F-AVR-07/04
1B OCR1BH OCR1BL
Bit
7
6
5
4
3
2
1
0 OCR1BH OCR1BL
OCR1B[15:8] OCR1B[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
16 TCNT1 OC1x 16 CPU 8 TEMP TEMP 16 P78 " 16 " 1 ICR1H ICR1L
Bit 7 6 5 4 ICR1[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 ICR1H ICR1L
ICR1[15:8]
ICP1( T/C1 ) TCNT1 ICR1 ICR1 TOP 16 CPU 8 TEMP TEMP 16 P78 " 16 " / TIMSK
Bit / 7 TOIE1 R/W 0 6 OCIE1A R/W 0 5 OCIE1B R/W 0 4 - R 0 3 ICIE1 R/W 0 2 OCIE0B R/W 0 1 TOIE0 R/W 0 0 OCIE0A R/W 0 TIMSK
* Bit 7 - TOIE1:T/C1 "1" I "1" T/C1 TIFR TOV1 CPU T/C1 (P42 " " ) * Bit 6 - OCIE1A: T/C1 A "1" I "1" T/C1 A TIFR1 OCF1A CPU T/C1 A (P42 " " ) * Bit 5 - OCIE1B: T/C1 B "1" I "1" T/C1 B TIFR1 OCF1B CPU T/C1 B (P42 " " ) * Bit 3 - ICIE1: T/C1 "1" I "1" T/C1 TIFR1 ICF1 CPU T/C1 (P42 " " ) T/C TIFR
Bit / 7 TOV1 R/W 0 6 OCF1A R/W 0 5 OCF1B R/W 0 4 - R 0 3 ICF1 R/W 0 2 OCF0B R/W 0 1 TOV0 R/W 0 0 OCF0A R/W 0 TIFR
102
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* Bit 7 - TOV1: T/C1 T/C1 CTC T/C1 TOV1 TOV1 P99Table 46 TOV1 "1" * Bit 6 - OCF1A: T/C1 A TCNT1 OCR1A "1" (FOC1A) OCF1A A OCF1A "1" * Bit 5 - OCF1B: T/C1 B TCNT1 OCR1B "1" (FOC1B) OCF1B B OCF1B "1" * Bit 3 - ICF1: T/C1 ICP1 ICF1 ICR1 TOP TOP ICF1 ICF1 "1"
103
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USART
(USART) * ( ) * * * * 5, 6, 7, 8, 9 1 2 * * * * * , * * Figure 52 USART CPU I/O I/O Figure 52. USART (1)
Clock Generator
UBRR[H:L] OSC
BAUD RATE GENERATOR
SYNC LOGIC
PIN CONTROL
XCK
Transmitter
UDR (Transmit) TX CONTROL PARITY GENERATOR TRANSMIT SHIFT REGISTER PIN CONTROL TxD
DATA BUS
Receiver
CLOCK RECOVERY RX CONTROL
RECEIVE SHIFT REGISTER
DATA RECOVERY
PIN CONTROL
RxD
UDR (Receive)
PARITY CHECKER
UCSRA
UCSRB
UCSRC
Note:
1. P2Figure 1P55Table 29 P53Table 26 USART
104
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ATtiny2313/V
USART XCK ( ) USART UDR AVR USART AVR UART USART AVR UART * * * * * * USART FIFO FE DOR 9 RXB8 UDR ( Figure 52) USART (DOR) CHR9 UCSZ2 OR DOR
*
: * *
USART 4 : USART C (UCSRC) ( ) UCSRA U2X (UMSEL = 1) XCK (DDR_XCK)()() XCK Figure 53 Figure 53.
UBRR fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 U2X
0 1
OSC DDR_XCK Sync Register Edge Detector
0 1
txclk
xcki XCK Pin xcko
0 1
UMSEL
DDR_XCK
UCPOL
1 0
rxclk
105
2543F-AVR-07/04
txclk rxclk xcki xcko fosc ( ) ( ) XCK ( ) XCK ( ). XTAL ( )
Figure 53 USART UBRR UBRRL UBRR fosc/(UBRR+1) 2 8 16 2 816 UMSEL U2X DDR_XCK Table 48(/)UBRR
106
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ATtiny2313/V
Table 48.
(U2X = 0) (U2X = 1) (1) UBRR
f OSC BAUD = --------------------------------------16 ( UBRR + 1 ) f OSC BAUD = -----------------------------------8 ( UBRR + 1 ) f OSC BAUD = -----------------------------------2 ( UBRR + 1 )
f OSC UBRR = ----------------------- - 1 16BAUD f OSC UBRR = -------------------- - 1 8BAUD f OSC UBRR = -------------------- - 1 2BAUD
Note:
1. (bps)
BAUD ( bps) fOSC UBRR UBRRH UBRRL (0-4095) Table 56 UBRR (U2X) UCSRA U2X "0" 16 8 Figure 53 XCK CPU XCK f OSC f XCK < -----------4 fosc
107
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(UMSEL = 1)XCK ( ) ( ) TxD XCK RxD Figure 54. XCK .
UCPOL = 1 XCK
RxD / TxD Sample UCPOL = 0 XCK
RxD / TxD Sample
UCRSC UCPOL XCK Figure 54 UCPOL=0 XCK XCK UCPOL=1 XCK XCK
( ) USART 30 * * * * 1 5 6 7 8 9 1 2
9 Figure 55 Figure 55.
FRAME
(IDLE)
St
0
1
2
3
4
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
(St / IDLE)
St (n) P Sp IDLE
(0 8) (RxD TxD)
UCSRB UCSRC UCSZ2:0 UPM1:0 USBS
108
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USART UCSZ2:0 UPM1:0 USBS (FE) "0" : P even = d n - 1 ... d 3 d 2 d 1 d 0 0 P odd = d n - 1 ... d 3 d 2 d 1 d 0 1 Peven Podd dn n
USART
USART USART ( ) USART TXC RXC ( UDR )TXC
109
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USART ( ) r17:r16 (1)
USART_Init: ; out out ldi out ldi out ret UBRRH, r17 UBRRL, r16 r16, (1<;
; : 8 , 2
C (1)
void USART_Init( unsigned int baud ) { /* */ UBRRH = (unsigned char)(baud>>8); UBRRL = (unsigned char)baud; /* */ UCSRB = (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
I/O
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USART UCSRB TXEN USART TxD
I/O USART XCK CPU UDR ( ) UDRE 8 UDR USART R16 (1)
USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; out ret UDR,r16
5 8
C (1)
void USART_Transmit( unsigned char data ) { /* */ while ( !( UCSRA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
UDRE
111
2543F-AVR-07/04
9
9 (UCSZ = 7) 9 UCSRB TXB8 8UDR 9 R17:R16 (1)(2)
USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; 9 r17 TXB8 cbi sbi out ret UCSRB,TXB8 UCSRB,TXB8 UDR,r16 sbrc r17,0 ; 8
C (1)(2)
void USART_Transmit( unsigned int data ) { /* */ while ( !( UCSRA & (1<Notes:
1. UCSRB UCSRB TXB8 2. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
9
112
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ATtiny2313/V
USART USART UDRE TXC UDRE "1" UCSRA "0" UCSRB UDRIE "1" UDRE ( ) USART UDR UDRE UDR UDRE TXC TXC "1" TXC RS-485 UCSRB TXCIE "1" TXC USART TXC TXC (UPM1 = 1) TXEN TxD I/O
113
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USART UCSRB (RXEN) USART RxD
USART XCK
5 8
XCK UDR RXC 8 UDR 0 USART (1)
USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; in ret r16, UDR
C (1)
unsigned char USART_Receive( void ) { /* */ while ( !(UCSRA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
RXC
114
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9 9 (UCSZ=7) UDR 8 UCSRB RXB8 9 FE DOR UPE UCSRA UDR UDR FIFO FIFO TXB8 FE DOR UPE USART 9 (1)
USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; 9 in in in r18, UCSRA r17, UCSRB r16, UDR
; -1 andi r18,(1<USART_ReceiveNoError: ; 9 lsr ret r17 andi r17, 0x01
C (1)
unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* */ while ( !(UCSRA & (1<> 1) & 0x01; return ((resh << 8) | resl); }
Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
I/O
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2543F-AVR-07/04
USART (RXC) 1 0( ) (RXEN = 0) RXC UCSRB (RXCIE) RXC ( ) USART UDR RXC
USART (FE) (DOR) (UPE) UCSRA UDR UCSRA (UDR) "0" (FE) ( 1) FE 0 FE 1 UCSRC USBS FE UCSRA 0 (DOR) ( ) DOR UDR UDR UCSRA 0 DOR (UPE) UPE UCSRA 0 P109" " P117" "
116
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ATtiny2313/V
UPM1 ( ) UPM0 (UPE) (UPM1 = 1) UPE (UDR) (RXEN ) RxD FIFO FIFO UDR RXC (1)
USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush
C (1)
void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
USART RxD
117
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Figure 56 16 8 (U2X = 1) RxD ( ) 0 Figure 56.
RxD IDLE START BIT 0
Sample
(U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Sample
(U2X = 1) 0 1 2 3 4 5 6 7 8 1 2
RxD ( ) ( ) 1 0 8 9 10( ) 4 5 6( ) ( ) 16 8 Figure 57 Figure 57.
RxD BIT n
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
(U2X = 1) 1 2 3 4 5 6 7 8 1
2 3 1 2 3 0RxD Figure 58
118
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ATtiny2313/V
Figure 58.
RxD STOP 1
(A) (B) (C)
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
Sample
(U2X = 1) 1 2 3 4 5 6 0/1
0 FE Figure 58 A B C ( Table 49) ( D + 1 )S R slow = --------------------------------------------S - 1 + D S + SF D S SF SM (D = 5 10 ) S = 16 S = 8 SF = 8 SF = 4 SM = 9 SM = 5 ( D + 2 )S R fast = ------------------------------------( D + 1 )S + S M
Rslow Rfast Table 49 Table 50
119
2543F-AVR-07/04
Table 49. (U2X = 0)
D # ( + ) 5 6 7 8 9 10 Rslow (%) 93.20 94.12 94.81 95.36 95.81 96.17 Rfast (%) 106.67 105.79 105.11 104.58 104.14 103.78 (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4.58/-4.54 +4.14/-4.19 +3.78/-3.83 (%) 3.0 2.5 2.0 2.0 1.5 1.5
Table 50. (U2X = 1)
D # ( + ) 5 6 7 8 9 10 Rslow (%) 94.12 94.92 95.52 96.00 96.39 96.70 Rfast (%) 105.66 104.92 104,35 103.90 103.53 103.23 (%) +5.66/-5.88 +4.92/-5.08 +4.35/-4.48 +3.90/-4.00 +3.53/-3.61 +3.23/-3.30 (%) 2.5 2.0 1.5 1.5 1.5 1.0
(XTAL) 2% UBRR
120
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UCSRA (MPCM) USART CPU MPCM 5 8 9 9 (RXB8) ( 9 ) 1 MPCM 9 (UCSZ = 7) (TXB8 = 1) 9 (TXB8) 1 (TXB = 0) 9 1. (UCSRA MPCM ) 2. UCSRA RXC 3. UDR UCSRA MPCM MPCM 1 4. MPCM 1 5. MPCM 2 5 8 n n+1 5 8 (USBS = 1) - - (SBI CBI) MPCM MPCM TXC I/O SBI CBI
USART
USART I/O UDR
Bit 7 6 5 4 RXB[7:0] TXB[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 UDR ( ) UDR ( )
USART USART I/O USART UDR UDR (TXB) UDR (RXB) 567 0 UCSRA UDRE UDRE UDR USART
121
2543F-AVR-07/04
TxD FIFO FIFO - - (SBI CBI) (SBIC SBIS) FIFO USART A UCSRA
Bit / 7 RXC R 0 6 TXC R/W 0 5 UDRE R 1 4 FE R 0 3 DOR R 0 2 UPE R 0 1 U2X R/W 0 0 MPCM R/W 0 UCSRA
* Bit 7 - RXC: USART RXC RXC RXC ( RXCIE ) * Bit 6 - TXC: USART (UDR) TXC TXC 1 TXC ( TXCIE )
122
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* Bit 5 - UDRE: USART UDRE(UDR) UDRE1 UDRE ( UDRIE ) UDRE * Bit 4 - FE: 0 FE (UDR) 1 FE 0 UCSRA 0 * Bit 3 - DOR: DOR ( ) (UDR) UCSRA 0 * Bit 2 - UPE: USART (UPM1 = 1) UPE (UDR) UCSRA 0 * Bit 1 - U2X: 1 16 8 * Bit 0 - MPCM: MPCM USART MPCM P121" "
123
2543F-AVR-07/04
USART B UCSRB
Bit /
7 RXCIE R/W 0
6 TXCIE R/W 0
5 UDRIE R/W 0
4 RXEN R/W 0
3 TXEN R/W 0
2 UCSZ2 R/W 0
1 RXB8 R 0
0 TXB8 R/W 0 UCSRB
* Bit 7 - RXCIE: RXC RXCIE 1 SREG UCSRA RXC 1 USART * Bit 6 - TXCIE: TXC TXCIE 1 SREG UCSRA TXC 1 USART * Bit 5 - UDRIE: USART UDRE UDRIE 1 SREG UCSRA UDRE 1 USART * Bit 4 - RXEN: USART RxD USART FE DOR UPE * Bit 3 - TXEN: USART TxD USART TXEN TxD I/O * Bit 2 - UCSZ2: UCSZ2UCSRCUCSZ1:0( ) * Bit 1 - RXB8: 8 9 RXB8 9 UDR RXB8 * Bit 0 - TXB8: 8 9 TXB8 9 UDR
124
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USART C UCSRC
Bit / 7 - R 0 6 UMSEL R/W 0 5 UPM1 R/W 0 4 UPM0 R/W 0 3 USBS R/W 0 2 UCSZ1 R/W 1 1 UCSZ0 R/W 1 0 UCPOL R/W 0 UCSRC
* Bit 6 - UMSEL: USART Table 51. UMSEL
UMSEL 0 1
* Bit 5:4 - UPM1:0: UPM0 UCSRA UPE Table 52. UPM
UPM1 0 0 1 1 UPM0 0 1 0 1
* Bit 3 - USBS: Table 53. USBS
USBS 0 1 1 2
* Bit 2:1 - UCSZ1:0: UCSZ1:0UCSRB UCSZ2( ) P126Table 54
125
2543F-AVR-07/04
Table 54. UCSZ
UCSZ2 0 0 0 0 1 1 1 1 UCSZ1 0 0 1 1 0 0 1 1 UCSZ0 0 1 0 1 0 1 0 1 5 6 7 8 9
* Bit 0 - UCPOL: UCPOL XCK Table 55. UCPOL
UCPOL 0 1 (TxD ) XCK XCK (RxD ) XCK XCK
USART UBRRL UBRRH
Bit
15 - 7
14 - 6 R R/W 0 0
13 - 5 R R/W 0 0
12 -
11
10
9
8 UBRRH UBRRL 0 R/W R/W 0 0
UBRR[11:8] 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0
UBRR[7:0] 4 R R/W 0 0 / R R/W 0 0
* Bit 15:12 - UBRRH * Bit 11:0 - UBRR11:0: USART 12 USART UBRRH USART 4 UBRRL 8 UBRRL
126
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ATtiny2313/V
Table 56 UBRR 0.5% ( P119" " )
BaudRate Closest Match Error[%] = ------------------------------------------------------- - 1 * 100% BaudRate
Table 56. UBRR
fosc = 1.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 1.
(1)
fosc = 1.8432 MHz U2X = 0 UBRR 47 23 11 7 5 3 2 1 1 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -25.0% 0.0% - - U2X = 1 UBRR 95 47 23 15 11 7 5 3 2 1 0 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% - 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - UBRR 51 25 12 8 6 3 2 1 1 0 - -
fosc = 2.0000 MHz U2X = 0 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - 125 kbps U2X = 1 UBRR 103 51 25 16 12 8 6 3 2 1 - 0 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% - 0.0% 250 kbps
U2X = 0 UBRR 25 12 6 3 2 1 1 0 - - - - 0.2% 0.2% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - - -
U2X = 1 UBRR 51 25 12 8 6 3 2 1 1 0 - - 125 kbps
62.5 kbps UBRR = 0, = 0.0%
115.2 kbps
230.4 kbps
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2543F-AVR-07/04
Table 57. UBRR
fosc = 3.6864 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 4.0000 MHz U2X = 1 U2X = 0 UBRR 103 51 25 16 12 8 6 3 2 1 0 0 - - 250 kbps 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% 8.5% 0.0% - - U2X = 1 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -
fosc = 7.3728 MHz U2X = 0 UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - U2X = 1 UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8%
U2X = 0 UBRR 95 47 23 15 11 7 5 3 2 1 0 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - -
UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 -
230.4 kbps UBRR = 0, = 0.0%
460.8 kbps
0.5 Mbps
460.8 kbps
921.6 kbps
128
ATtiny2313/V
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ATtiny2313/V
Table 58. UBRR
fosc = 8.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 11.0592 MHz U2X = 0 UBRR 287 143 71 47 35 23 17 11 8 5 2 2 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 575 287 143 95 71 47 35 23 17 11 5 5 2 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0
fosc = 14.7456 MHz U2X = 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8% U2X = 1 UBRR 767 383 191 127 95 63 47 31 23 15 7 6 3 1 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 5.3% -7.8% -7.8%
U2X = 0 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% -
U2X = 1 UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0
0.5 Mbps UBRR = 0, = 0.0%
1 Mbps
691.2 kbps
1.3824 Mbps
921.6 kbps
1.8432 Mbps
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Table 59. UBRR
fosc = 16.0000 MHz U2X = 0 (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
U2X = 1 UBRR -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% 832 416 207 138 103 68 51 34 25 16 8 7 3 1 2 Mbps 0.0% -0.1% 0.2% -0.1% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% -3.5% 0.0% 0.0% 0.0%
UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0
1 Mbps UBRR = 0, = 0.0%
130
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USI
USI USI USI * ( , fSCLmax = fCK/16) * ( fSCKmax = fCK/4) * * * * Figure 59.USI I/O P2"ATtiny2313" CPU I/O I/O P137"USI " Figure 59.
DQ LE
DO (Output only)
DI/SDA
Bit7 Bit0
(Input/Open Drain)
USIDR
3 2 1 0 TIM0 COMP
USIOIF
USISIF
USIDC
USIPF
4-bit Counter
3 2 1 0 [1]
0 1
CLOCK HOLD
USCK/SCL
(Input/Open Drain)
DATA BUS
USISR
Two-wire Clock Control Unit
2
USIWM1
USIWM0
USICS1
USICS0
USICLK
USIOIE
USISIE
USICR
8 (DI) 4 USCK 0
USI(SPI)01 (SS) DI DO USCK
USITC
131
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Figure 60.
DO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DI
USCK SLAVE
DO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DI
USCK PORTxn MASTER
Figure 60 USI 8 USCK USI 4 ( ) USIOI USCK USICR USITC Figure 61.
CYCLE USCK USCK DO DI
MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
( Reference ) 1 2 3 4 5 6 7 8
A
B
C
D
E
Figure 61. USCK USI (USIDR) USCK 0(USICS0 = 0) DI DO ( ) 1(USICS0 = 1) 0 USI SPI 0 1 Figure 61. 1. A B
132
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C USCK 4 0 2. USCK (C D) (DI) USI (C) (D) 4 3. ( ) 2 8 4. 8 (16 ) SPI USI SPI
SPITransfer: out ldi out ldi out sbis rjmp in ret USIDR,r16 r16,(1<SPITransfer_loop:
8 (+ ret) DO USCK DDRE r16 r16 USI USI USITC USCK 16
133
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(fsck = fck/2) USI SPI
SPITransfer_Fast: out ldi ldi out out out out out out out out out out out out out out out out in ret USIDR,r16 r16,(1<SPI
USI SPI
init: ldi out ... SlaveSPITransfer: out ldi out sbis rjmp in ret USIDR,r16 r16,(1<SlaveSPITransfer_loop:
8 (+ ret) DO USCK DDR r16 r16 USI 134
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USI IC (TWI) SCL SDA Figure 62.
VCC
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SDA
SCL
HOLD SCL
Two-wire Clock Control Unit SLAVE
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SDA
SCL PORTxn MASTER
Figure 62 USI SCL SCL PORT USCK TWI Figure 63.
SDA SCL
S 1-7 ADDRESS 8 R/W 9 ACK 1-8 DATA 9 ACK 1-8 DATA 9 ACK P
A
B
C
D
E
F
(Figure 63.) 1. SCL (A) SDA SDA 7 0 PORT 0
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(Figure 64.) USISIF 2. SCL (B) SCL 3. SCL (C) SCL 4. ()8 SCL (D) SCL 5. SCL ( SCL(D) 14) SDA R/W R/W 1 ( SDA ) (E) SCL 6. (F) Figure 64.
USISIF DQ SDA
CLR CLR
DQ
CLOCK HOLD
SCL Write( USISIF)
136
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Figure 64. SDA (50 300 ns) SCL SCL CKSEL P21" "
USI
4 12 /
USI UART 4 USI 4 / 0 12 (F) USICS1
USI
USI USIDR
Bit / 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 USIDR
USI USIDR USICS1..0 / 0 USICLK (USIWM1..0 = 0) (DI/SDA) (USCK/SCL) (DO SDA ) ( 7) (USICS1 = 1) ( ) (USICS1 = 0) MSB USI USISR
Bit / 7
USISIF
6
USIOIF
5
USIPF
4
USIDC
3
USICNT3
2
USICNT2
1
USICNT1
0
USICNT0 USISR
R/W 0
R/W 0
R/W 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bit 7 - USISIF: USISIF (USICSx = 0b11 & USICLK = 0) (USICS = 0b10 & USICLK = 0) SCK
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USISIF USICR USISIE USISIF 1 USCL * Bit 6 - USIOIF: 4(150) USICRUSIOIE USIOIF 1 SCL * Bit 5 - USIPF: USIPF USIOIF 1 * Bit 4 - USIDC: 7 USIDC * Bits 3..0 - USICNT3..0: 4 CPU / 0 USICLK USITC USICS1..0 USITC (USICS1 = 1) USICLK 1 (USIWM1..0 = 0) (USCK/SCL) USI USICR
Bit / 7 USISIE R/W 0 6 USIOIE R/W 0 5 USIWM1 R/W 0 4 USIWM0 R/W 0 3 USICS1 R/W 0 2 USICS0 R/W 0 1 USICLK W 0 0 USITC W 0 USICR
* Bit 7 - USISIE: 1 USISIE * Bit 6 - USIOIE: 1 USIOIE * Bit 5..4 - USIWM1..0: USIWM1..0 USI P139Table 60
138
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ATtiny2313/V
Table 60. USIWM1..0 USI
USIWM1 0 0 USIWM0 0 1 DO DI USCK (DO) IO DDR PORT (DI) (USCK) PORT USICR USITC SDA (DI) SCL (USCK) (1) (SDA) (SCL) DDR SDA PORT 0 SDA SDA ( ) SCL PORT 0 SCL SCL SCL (USISIF) SDA SCL SDA SCL SDA SCL SCL (USIOIF)
1
0
1
1
Note:
1. USCK (SDA) (SCL ) DI
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2543F-AVR-07/04
* Bit 3..2 - USICS1..0: (USCK/SCL) (DI/SDA) / 0 USICS1..0 0 USICLK 1 (USICS1 = 1) USICLK USITC Table 61 USICS1..0 USICLK 4 Table 61. USICS1..0 USICLK
USICS1 0 0 0 1 1 1 1 USICS0 0 0 1 0 1 0 1 USICLK 0 1 X 0 0 1 1 (USICLK) / 0 4 (USICLK) / 0 (USITC) (USITC)
* Bit 1 - USICLK: USICS1..0 0 USICLK 0 (USICS1 = 1) USICLK USICLK USITC 4 ( Table 61) * Bit 0 - USITC: USITC USCK/SCL 01 DDRE4 0 (USICS1 = 1) USICLK 1 USITC 4
140
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ATtiny2313/V
AIN0 AIN1 AIN0 AIN1 ACO / 1 Figure 65 Figure 65.
BANDGAP REFERENCE ACBG
ACSR
Bit /
7 ACD R/W 0
6 ACBG R/W 0
5 ACO R N/A
4 ACI R/W 0
3 ACIE R/W 0
2 ACIC R/W 0
1 ACIS1 R/W 0
0 ACIS0 R/W 0 ACSR
* Bit 7 - ACD: ACD ACD ACSR ACIE ACD * Bit 6 - ACBG: ACBG "1" ACBG AIN0 P36 " " * Bit 5 - ACO: ACO 1 - 2 * Bit 4 - ACI: ACIS1 ACIS0 ACI ACIE SREG I ACI ACI 1 * Bit 3 - ACIE: ACIE 1 I * Bit 2 - ACIC: T/C1 T/C1 T/C1 (TIMSK) ICIE1
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* Bits 1, 0 - ACIS1, ACIS0: Table 62 Table 62. ACIS1/ACIS0
ACIS1 0 0 1 1 ACIS0 0 1 0 1
ACIS1/ACIS0 ACSR DIDR
Bit / 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 AIN1D R/W 0 0 AIN0D R/W 0 DIDR
* Bit 1, 0 - AIN1D, AIN0D: AIN1, AIN0 "1" AIN1/0 AIN1/0 "1"
142
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debugWIRE
* * * * * * * * * *
RESET (C HLL) ( )

debugWIRE CPU AVR debugWIRE DWEN debugWIRE RESET ( ) I/O Figure 66. debugWIRE
1.8 - 5.5V
VCC
dW
dW(RESET)
GND
Figure 66 debugWIRE MCU debugWIRE CKSEL debugWIRE * * * * dW/(RESET) 10k debugWIRE RESET VCC debugWIRE RESET
143
2543F-AVR-07/04
debugWIRE AVR AVR Studio(R) BREAK BREAK BREAK Flash AVR Studio(R) debugWIRE Flash
debugWIRE
debugWIRE (dW) (RESET) debugWIRE CPU debugWIRE I/O CPU I/O debugWIRE DWEN debugWire DWEN
I/O debugWIRE
debugWire DWDR
debugWire
Bit /
7 R/W 0
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 R/W 0
0 DWDR R/W 0
DWDR[7:0]
DWDR MCU debugWIRE
144
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Flash
MCU ( ) SPM 1 * * * * * *
2
( ) 1 Boot Loader - - 2 SPM Z "00000011" SPMCSR SPMR1 R0 Z PCPAGE Z * ( ) CPU
Z R1:R0 "00000001" SPMCSR SPM Z PCWORD SPMCSRCTPB SPM EEPROM
Z "00000101" SPMCSR SPMR1 R0 Z PCPAGE Z * CPU
145
2543F-AVR-07/04
Flash
Z SPM
Bit ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0
Flash ( P152Table 69) Figure 67 Boot Loader LPMZ ZLSB ( Z0) Figure 67. SPM (1)
BIT Z - REGISTER PCMSB PROGRAM COUNTER
PCPAGE
15
ZPCMSB
ZPAGEMSB
10 0
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. Figure 67 P152Table 69
146
ATtiny2313/V
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(SPM) SPMCSR Boot Loader SPMCSR
Bit 7
-
6
-
5
-
4
3
2
1
PGERS
0
SELFPRGEN SPMCSR
CTPB
RFLB
PGWRT
/
R 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* Bits 7..5 - Res: ATtiny2313 "0" * Bit 4 - CTPB: CTPB * Bit 3 - RFLB: SPMCSR RFLB SELFPRGEN LPM ( Z Z0 ) P148"EEPROM SPMCSR " * Bit 2 - PGWRT: SELFPRGEN SPM Flash Z R1 R0 SPM PGWRT CPU * Bit 1 - PGERS: SELFPRGEN SPM Z R1 R0 SPM PGERS CPU * Bit 0 - SELFPRGEN: SPM CTPB RFLB PGWRT PGERS SPM SELFPRGEN SPM R1:R0 Z Z LSB SPM SPM SPMEN SELFPRGEN "10001" "01001" "00101" "00011" "00001"
147
2543F-AVR-07/04
EEPROM SPMCSR
EEPROM Flash SPMCSR EECR EEWE 0x0001 Z SPMCSR RFLB SELFPRGEN RFLB SELFPRGEN CPU LPM CPU LPM CPU SPM RFLB SELFPRGEN RFLB SELFPRGEN LPM
Bit Rd 7 - 6 - 5 - 4 - 3 - 2 - 1 LB2 0 LB1
0x0000ZSPMCSRRFLB SELFPRGEN SPMCSR CPU LPM (FLB) P152Table 68 .
Bit Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0
0x0003 Z SPMCSR RFLB SELFPRGEN SPMCSR CPU LPM (FHB)
Bit Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0
/ "0" / "1"
148
ATtiny2313/V
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ATtiny2313/V
Flash VCC CPU Flash Flash Flash Flash Flash CPU Flash ( ) 1. AVR RESET BOD 2. AVR CPU SPMCSR Flash SPM Flash RC Flash Table 63 CPU Flash Table 63. SPM
Flash ( SPM ) 3.7 ms 4.5 ms
149
2543F-AVR-07/04
ATtiny2313 2 ("0") ("1") Table 65 "1"
Table 64. (1)
7 6 5 4 3 2 LB2 LB1 Note: 1 0 - - - - - - 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( )
1. "1" "0"
Table 65. (1)(2)
LB 1 2 3 Notes: LB2 1 1 0 LB1 1 0 0 Flash EEPROM (1) Flash EEPROM (1)
1. LB1 LB2 Boot 2. "1" , "0"
150
ATtiny2313/V
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ATtiny2313/V
ATtiny2313 Table 67 Table 68 "0" Table 66.
7 6 5 4 3 2 1 SELFPRGEN 0 - - - - - - - 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( )
Table 67.
DWEN
(3)
7 6 5 4
debugWIRE EEPROM BOD BOD BOD
1 ( ) 1 ( EEPROM ) 0 ( SPI ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( )
EESAVE SPIEN(1) WDTON
(2) (4) (4)
BODLEVEL2 BODLEVEL1
3 2 1 0
BODLEVEL0(4) RSTDISBL Note:
(5)
1. SPIEN 2. P40" WDTCSR" 3. DWEN DWEN 4. P33Table 16 BODLEVEL 5. RSTDISBL P51" A "
151
2543F-AVR-07/04
Table 68.
CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Note: 7 6 5 4 3 2 1 0 8 0 ( ) 1 ( ) 1 ( )(1) 0 ( )(1) 0 ( )(2) 0 ( )(2) 1 ( )(2) 0 ( )(2)
1. SUT1..0 P32Table 15 2. CKSEL3..0 RC 8 MHz
1(LB1) EESAVE Atmel ATtiny2313 1. 0x000: 0x1E ( Atmel l) 2. 0x001: 0x91 ( 2KB Flash ) 3. 0x002: 0x0A ( 0x001 0x91 ATmega48)
ATtiny2313 RC 0x000 0x0001 4 8 MHz 4 MHz OSCCAL RC
Table 69.
Flash
16 PCWORD PC[3:0] 64 PCPAGE PC[9:4] PCMSB 9
Flash 1K (2K )
Table 70.
EEPROM
4 PCWORD EEA[1:0] 32 PCPAGE EEA[6:2] EEAMSB 6
EEPROM 128
ATtiny2313 Flash EEPROM 250 ns
152
ATtiny2313/V
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ATtiny2313/V
ATtiny2313 Figure 68 Table 71 XA1/XA0 XTAL1 Table 73 WR OE Table 74 Figure 68.
+5V RDY/BSY OE WR BS1/PAGEL XA0 XA1/BS2 PD1 PD2 PD3 PD4 PD5 PD6
PB7 - PB0
VCC
DATA I/O
+12 V
RESET
XTAL1 GND
Table 71.
RDY/BSY OE WR BS1/PAGEL XA0 XA1/BS2 DATA I/O PD1 PD2 PD3 PD4 PD5 PD6 PB7-0 I/O O I I I I I I/O 0: , 1: ( ). ( ). 1("0" , "1" ). XTAL 0 XTAL 1 2 ("0" , "1" ) (OE )
Table 72.
XA1 XA0 BS1 WR Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] 0 0 0 0
153
2543F-AVR-07/04
Table 73. XA1 XA0
XA1 0 0 1 1 XA0 0 1 0 1 XTAL1 Flash EEPROM ( BS1 ) ( BS1 Flash )
Table 74.
1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Flash EEPROM Flash EEPROM
Table 75.
MOSI MISO SCK PB5 PB6 PB7 I/O I O I t
1. VCC GND 4.5 - 5.5V 2. RESET XTAL1 6 3. P153Table 72 Prog_enable "0000" 100 ns 4. RESET 11.5 - 12.5V RESET +12V 100 ns Prog_enable 5. 50 s * * 0xFF Flash EEPROM( EESAVE )
154
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ATtiny2313/V
* Flash EEPROM 256
Flash EEPROM(1) Flash / EEPROM
Note: 1. EESAVE EEPRPOM
" " 1. XA1 XA0 "10" 2. BS1 "0" 3. DATA "1000 0000" 4. XTAL1 5. WR RDY/BSY 6. RDY/BSY
155
2543F-AVR-07/04
Flash
Flash P152Table 69 Flash Flash A. " Flash" 1. XA1 XA0 "10" 2. BS1 "0" 3. DATA "0001 0000" Flash 4. XTAL1 B. 1. XA1 XA0 "00" 2. BS1 "0" 3. DATA (0x00 - 0xFF) 4. XTAL1 C. 1. XA1 XA0 "01" 2. DATA (0x00 - 0xFF) 3. XTAL1 D. 1. BS1 "1" 2. XA1 XA0 "01" 3. DATA (0x00 - 0xFF) 4. XTAL1 E. 1. BS1 "1" 2. PAGEL ( Figure 70 ) F. B E FLASH P157Figure 69 8 ( < 256) G. 1. XA1 XA0 "00" 2. BS1 "1" 3. DATA (0x00 - 0xFF) 4. XTAL1 H. 1. WR RDY/BSY RDY/BSY ( Figure 70 ) I. B H Flash J. 1. 1. XA1 XA0 "10" 2. DATA "0000 0000"
156
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3. XTAL1 Figure 69. Flash (1)
PCMSB PROGRAM COUNTER
PCPAGE
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. PCPAGE PCWORD P152Table 69
Figure 70. Flash (1)
F
A
DATA 0x10
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
G
ADDR. HIGH
H
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note:
1. "XX" Flash
157
2543F-AVR-07/04
EEPROM
P152Table 70 EEPROM EEPROM EEPROM ( P156" Flash " ) 1. A "0001 0001" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. C (0x00 - 0xFF) 5. E ( PAGEL ) K 3 5 L EEPROM 1. BS "0" 2. WR EEPROM RDY/BSY 3. RDY/BSY ( Figure 71 ) Figure 71. EEPROM
K
A
DATA 0x11
G
ADDR. HIGH
B
ADDR. LOW
C
DATA
E
XX
B
ADDR. LOW
C
DATA
E
XX
L
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Flash
Flash ( P156" Flash " ) 1. A "0000 0010" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE "0" BS1 "0" DATA Flash 5. BS "1" DATA Flash 6. OE "1"
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EEPROM ( P156" Flash " ) 1. A "0000 0011" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE "0" BS1 "0" DATA EEPROM 5. OE "1" ( P156" Flash " ) 1. A "0100 0000" 2. C "0" 3. WR RDY/BSY ( P156" Flash " ) 1. A "0100 0000" 2. C "0" 3. BS1 "1" BS2 "0" 4. WR RDY/BSY 5. BS1 "0" ( P156" Flash " ) 1. A "0100 0000" 2. C "0" 3. 3. BS1 "0" BS2 "1" 4. 4. WR RDY/BSY 5. 5. BS2 "0" Figure 72.
Write Fuse Low byte A
DATA
0x40
Write Fuse high byte A C
DATA XX
Write Extended Fuse byte A
0x40
C
DATA XX
C
DATA XX
0x40
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
( P156" Flash " ) 1. A "0010 0000" 2. C. n "0" LB 3(LB1 LB2 )
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2543F-AVR-07/04
3. WR RDY/BSY ( P156" Flash " ) 1. A "0000 0100" 2. OE BS2 BS1 "0" DATA ("0" ) 3. OE "0" BS2 BS1 "1" DATA ("0" ) 4. OE BS1 "0" BS2 "1" DATA ("0" ) 5. OE "0" BS2 "0" BS1 "1" DATA ("0" ) 6. OE "1" Figure 73. BS1 BS2
Fuse Low Byte 0
0 Extended Fuse Byte BS2 Lock Bits 0 1 1 DATA
Fuse High Byte BS2
1
BS1
( P156" Flash " ) 1. A "0000 1000" 2. B 0x00 - 0x02 3. OE "0" BS1 "1" DATA 4. OE "1"
160
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ATtiny2313/V
( P156" Flash " ) 1. A "0000 1000" 2. B 0x00 3. OE "0" BS1 "1" DATA 4. OE "1" Figure 74.
tXLWL XTAL1 tDVXH Data & Contol (DATA, XA0/1, BS1, BS2) tBVPH PAGEL WR RDY/BSY tWLRH tPHPL tWLWH tPLWL
WLRL
tXHXL tXLDX
tPLBX t BVWL
tWLBX
Figure 75. (1)
LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE)
t XLXH
LOAD DATA LOAD DATA (HIGH BYTE)
tXLPH tPLXH
LOAD ADDRESS (LOW BYTE)
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. Figure 74 (tDVXH tXHXL tXLDX)
161
2543F-AVR-07/04
Figure 76. ( )(1)
LOAD ADDRESS (LOW BYTE)
tXLOL
READ DATA (LOW BYTE)
READ DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
XTAL1
tBVDV
BS1
tOLDV
OE
tOHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. Figure 74 ( tDVXH tXHXL tXLDX)
Table 76. VCC = 5V 10%
VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tXLPH tPLXH tBVPH tPHPL tPLBX tWLBX tPLWL tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 WR XTAL1 PAGEL PAGEL XTAL1 PAGEL BS1 PAGEL PAGEL BS1 WR BS2/1 PAGEL WR BS1 WR WR WR RDY/BSY WR RDY/BSY (1) WR RDY/BSY XTAL1 OE
(2)
11.5

12.5 250
V A ns ns ns ns ns ns ns ns ns ns ns ns ns ns
67 200 150 67 0 0 150 67 150 67 67 67 67 150 0 3.7 7.5 0 1 4.5 9
s ms ms ns
162
ATtiny2313/V
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ATtiny2313/V
Table 76. VCC = 5V 10%
tBVDV tOLDV tOHDZ Notes: BS1 DATA OE DATA OE DATA 1. Flash EEPROM tWLRH 2. tWLRH_CE 0 250 250 250 ns ns ns
RESET SPI Flash EEPROM SCK MOSI( ) MISO( ) RESET P154Table 75 SPI SPI SPI Figure 77. (1)
+1.8 - 5.5V VCC
MOSI MISO SCK XTAL1
RESET
GND
Notes:
1. XTAL1 2. VCC - 0.3V < AVCC < VCC + 0.3V AVCC 1.8 - 5.5V
EEPROM MCU EEPROM 0xFF CKSEL (SCK) fck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU > fck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU >
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ATtiny2313 SCK ATtiny2313 SCK Figure 78 Figure 79 Table 79 ATtiny2313 ( P165Table 78 4 ) 1. RESET SCK "0" VCC GND SCK SCK RESET 2 CPU 2. 20 ms MOSI 3. (0x53) 4 0x53 RESET 4. Flash 4 LSB 8 tWD_FLASH ( P165Table 77.) Flash 5. A: EEPROM EEPROM tWD_EEPROM ( P165Table 77.) 0xFF B:EEPROM Load EEPROM 2 LSB EEPROM EEPROM 5 MSB EEPROM Load EEPROM tWD_FLASH ( P165Table 77) 0xFF 6. MISO 7. RESET 8. ( ) RESET "1" VCC
164
ATtiny2313/V
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ATtiny2313/V
Table 77. Flash EEPROM
tWD_FLASH tWD_EEPROM tWD_ERASE tWD_FUSE 4.5 ms 4.0 ms 4.0 ms 4.5 ms
Figure 78.
SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK)
SAMPLE
MSB
LSB
MSB
LSB
Table 78.
1 1010 1100 1010 1100 0010 H000 0100 H000 2 0101 0011 100x xxxx 0000 00aa 000x xxxx 3 xxxx xxxx xxxx xxxx bbbb bbbb xxxx bbbb 4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii RESET EEPROM Flash a:b H( ) o b H( ) i a:b EEPROM a:b o EEPROM b i i EEPROM EEPROM b EEPROM "0" "1" P150Table 64 "0" P150Table 64 b o
EEPROM EEPROM EEPROM ( ) EEPROM( )
0100 1100 1010 0000 1100 0000 1100 0001
0000 00aa 000x xxxx 000x xxxx 0000 0000
bbbb xxxx xbbb bbbb xbbb bbbb 0000 00bb
xxxx xxxx oooo oooo iiii iiii iiii iiii
1100 0010 0101 1000 1010 1100 0011 0000
00xx xxxx 0000 0000 111x xxxx 000x xxxx
xbbb bb00 xxxx xxxx xxxx xxxx xxxx xxbb
xxxx xxxx xxoo oooo 11ii iiii oooo oooo
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Table 78.
RDY/BSY Note: 1 1010 1100 1010 1100 1010 1100 0101 0000 0101 1000 0101 0000 0011 1000 1111 0000 2 1010 0000 1010 1000 1010 0100 0000 0000 0000 1000 0000 1000 000x xxxx 0000 0000 3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 000b xxxx xxxx 4 iiii iiii iiii iiii xxxx xxxi oooo oooo oooo oooo oooo oooo oooo oooo xxxx xxxo "0" "1" . "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" b o = "1" "0"
a = b = H = 0 - 1 - o = i = x =
166
ATtiny2313/V
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ATtiny2313/V
Figure 79.
MOSI tOVSH SCK MISO tSLIV tSHSL tSHOX tSLSH
Table 79. A = -40C 85C, VCC = 2.7V - 5.5V ( ) T
1/tCLCL tCLCL 1/tCLCL tCLCL tSHSL tSLSH tOVSH tSHOX tSLIV Note: (ATtiny2313L) (ATtiny2313L) (ATtiny2313, VCC = 4.5V - 5.5V) (ATtiny2313, VCC = 4.5V - 5.5V) SCK SCK MOSI SCK SCK MOSI SCK MISO 1. fck < 12 MHz 2 tCLCL fck >= 12 MHz 3 tCLCL 0 125 0 67 2 tCLCL* 2 tCLCL* tCLCL 2 tCLCL TBD TBD TBD 16 8 MHz ns MHz ns ns ns ns ns ns
167
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*
........................................................ -55C +125C ........................................................ -65C +150C RESET............ -0.5V VCC+0.5V RESET .................................. -0.5V +13.0V .................................................................... 6.0V I/O ......................................... 40.0 mA *NOTICE: " "
VCC GND ................................ 200.0 mA
VIL VIH VIH2 VOL VOH IIL IIH RRST Rpu
TA = -40C 85C, VCC = 1.8V 5.5V ( )(1)
( B)
(4)
RESET RESET IOL = 10 mA, VCC = 5V IOL = 5 mA, VCC = 3V IOH = -10 mA, VCC = 5V IOH = -5 mA, VCC = 3V Vcc = 5.5V, ( ) Vcc = 5.5V, ( )
-0.5 0.6VCC(3) 0.9VCC(3)
0.2VCC VCC +0.5 VCC +0.5 0.7 0.5
V V V V V V V
(5) ( B) I/O I/O Reset I/O
4.2 2.5 1 1 30 20 60 50 0.35 2 6 0.08 0.41 1.6 <3 < 0.5 0.2 1 3 6 2
A A k k mA mA mA mA mA mA A A
1MHz, VCC = 2V 4MHz, VCC = 3V ICC 8MHz, VCC = 5V 1MHz, VCC = 2V 4MHz, VCC = 3V 8MHz, VCC = 5V Notes: WDT , VCC = 3V WDT , VCC = 3V
1. AVR 2. " " 3. " "
168
ATtiny2313/V
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ATtiny2313/V
4. ()I/O(20 mA CC = 5V10 mAVCC = 3V) V 1] IOL 60 mA IOL VOL 5. ( ) I/O (20 mA CC = 5V 10 mAVCC = 3V) V 1] IOH 60 mA IOH VOH
Figure 80.
V IH1 V IL1
Table 80. ( )
VCC=1.8-5.5V 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL 0 1000 400 400 2.0 2.0 2 1 0 125 50 50 1.6 1.6 2 8 VCC=4.5-5.5V 0 62.5 25 25 0.5 0.5 2 16 MHz ns ns ns s s %
tCLCL
169
2543F-AVR-07/04
VCC
VCC Figure 81 Figure 82 VCC 1.8V < VCC < 2.7V 2.7V < VCC < 4.5V Figure 81. ATTINY2313V VCC
10 MHz
Safe Operating Area
4 MHz
1.8V
2.7V
5.5V
Figure 82. ATtiny2313 VCC
20 MHz
10 MHz
Safe Operating Area
2.7V
4.5V
5.5V
170
ATtiny2313/V
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ATtiny2313/V
ATtiny2313
I/O I/O I/O I/O CL*VCC*f CL = VCC = f = I/O Figure 83. (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz 1.2
1
5.5 V 5.0 V
0.8
4.5 V 4.0 V 3.3 V
ICC (mA)
0.6
0.4
2.7 V 1.8 V
0.2
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz)
171
2543F-AVR-07/04
Figure 84. (1 - 20 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz
14
5.5 V
12 10
ICC (mA)
5.0 V 4.5 V
8 6 4 2
4.0 V 3.3 V 2.7 V 1.8 V
0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz)
Figure 85. VCC ( RC 8 MHz)
ACTIVE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 8 MHz 10 9 8 7 6 Icc (mA) 5 4 3 2 1 0 1.5 2 2.5 3 3.5 Vcc (V) 4 4.5 5 5.5 -40 C 85 C 25 C
172
ATtiny2313/V
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ATtiny2313/V
Figure 86. VCC ( RC 4 MHz)
ACTIVE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 4 MHz 6 -40 C 25 C 85 C
5
4 Icc (mA)
3
2
1
0 1.5 2 2.5 3 3.5 Vcc (V) 4 4.5 5 5.5
Figure 87. VCC ( RC 1 MHz)
ACTIVE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 1 MHz 2 1.8 1.6 1.4 1.2 Icc (mA) 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 Vcc (V) 4 4.5 5 5.5 85 C 25 C -40 C
173
2543F-AVR-07/04
Figure 88. VCC ( RC 0.5 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 0.5 MHz 1.2
1
85 C 25 C -40 C
0.8
ICC (mA)
0.6
0.4
0.2
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5 6
Figure 89. VCC ( RC 128 KHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 128 KHz 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
-40 C 25 C 85 C
174
ATtiny2313/V
2543F-AVR-07/04
ICC (mA)
ATtiny2313/V
Figure 90. (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz 0.25
5.5 V
0.2
5.0 V 4.5 V
0.15
ICC (mA)
4.0 V 3.3 V 2.7 V
0.1
0.05
1.8 V
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz)
Figure 91. (1 - 20 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz 6
5
5.5 V
4
5.0 V 4.5 V
ICC (mA)
3
2
1
4.0 V 3.3 V 2.7 V 1.8 V
0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz)
0
175
2543F-AVR-07/04
Figure 92. VCC ( RC 8 MHz)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 8 MHz 3.5 3 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 3.5 Vcc (V) 4 4.5 5 5.5
85 C 25 C -40 C
Figure 93. VCC ( RC 4 MHz)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 4 MHz 1.8 1.6 1.4 1.2 85 C 25 C -40 C
Icc (mA)
Icc (mA)
1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 V cc (V) 4 4.5 5 5.5
176
ATtiny2313/V
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ATtiny2313/V
Figure 94. VCC ( RC 1 MHz)
IDLE SUPPLY CURRENT vs. Vcc
INTERNAL RC OSCILLATOR, 1 MHz 0.6
0.5
85 C 25 C -40 C
0.4 Icc (mA)
0.3
0.2
0.1
0 1.5 2 2.5 3 3.5 Vcc (V) 4 4.5 5 5.5
Figure 95. VCC ( RC 0.5 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 0.5 MHz 0.35 0.3 0.25 0.2 0.15 0.1 0.05 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
85 C 25 C -40 C
ICC (mA)
177
2543F-AVR-07/04
Figure 96. VCC ( RC 128 KHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 128 KHz 0.035 0.03 0.025 0.02 0.015 0.01 0.005 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
-40 C 25 C 85 C
Figure 97. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER DISABLED 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 3.5 Vcc (V) 4 4.5 5 5.5 85 C
ICC (mA)
I cc (uA)
-40 C 25 C
178
ATtiny2313/V
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ATtiny2313/V
Figure 98. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. Vcc
WATCHDOG TIMER ENABLED 25
20
85 C 25 C -40 C
15 Icc (uA)
10
5
0 1.5 2 2.5 3 3.5 Vcc (V) 4 4.5 5 5.5
Standby
Figure 99. Standby VCC
STANDBY SUPPLY CURRENT vs. VCC
0.08 0.07 0.06
455KHz Res 2MHz Res 2MHz Xtal
0.05
ICC (mA)
1MHz Res
0.04 0.03 0.02 0.01 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
179
2543F-AVR-07/04
Figure 100. I/O (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 5V 120
-40 C
100
25 C 85 C
80
IRESET (uA)
60
40
20
0 0 1 2 3 VRESET (V) 4 5 6
Figure 101. I/O (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7V 80
85 C 25 C
70 60 50
-40 C
IOP (uA)
40 30 20 10 0 0 0.5 1 1.5 VOP (V) 2 2.5 3
180
ATtiny2313/V
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ATtiny2313/V
Figure 102. (Reset) Reset (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 5V 120
-40 C
100
25 C 85 C
80
IRESET (uA)
60
40
20
0 0 1 2 3 VRESET (V) 4 5 6
Figure 103. (Reset) Reset (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 2.7V 60
-40 C
50
25 C 85 C
40
IRESET (uA)
30
20
10
0 0 0.5 1 1.5 VRESET (V) 2 2.5 3
181
2543F-AVR-07/04
Figure 104. I/O (VCC = 5V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 5V 90 80 70 60
-40 C 25 C 85 C
IOH (mA)
50 40 30 20 10 0 2.5 3 3.5 VOH (V) 4 4.5 5
Figure 105. I/O (VCC = 2.7V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V 30
-40 C
25
25 C 85 C
20
IOH (mA)
15
10
5
0 0.5 1 1.5 VOH (V) 2 2.5 3
182
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ATtiny2313/V
Figure 106. I/O (VCC = 1.8V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 1.8V 9
-40 C 85 C
25 C8
7 6
IOH (mA)
5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 VOH (V) 1.2 1.4 1.6 1.8 2
Figure 107. I/O (VCC = 5V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 5V 90 80 70 60
-40 C 25 C 85 C
IOL (mA)
50 40 30 20 10 0 0 0.5 1 VOL (V) 1.5 2 2.5
183
2543F-AVR-07/04
Figure 108. I/O (VCC = 2.7V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
VCC = 2.7V 35
-40 C
30
25
25 C 85 C
IOL (mA)
20
15
10
5
0 0 0.5 1 VOL (V) 1.5 2 2.5
Figure 109. I/O (VCC = 1.8V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 1.8V 14
12
-40 C 25 C 85 C
10
IOL (mA)
8
6
4
2
0 0 0.2 0.4 0.6 0.8 1 VOL (V) 1.2 1.4 1.6 1.8 2
184
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Figure 110. I/O (VCC = 5V)
RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V 16 14 12 10 8
-40 C
25 C
Current (mA)
85 C
6 4 2 0 0 1 2 3 VOH (V) 4 5 6
Figure 111. I/O (VCC = 2.7V)
RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V 4.5
-40 C
4 3.5
25 C
3
Current (mA)
2.5 2
85 C
1.5 1 0.5 0 0 0.5 1 1.5 VOH (V) 2 2.5 3
185
2543F-AVR-07/04
Figure 112. I/O (VCC = 1.8V)
RESET I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE
Vcc = 1.8V 1.4
-40 C
1.2
25 C
1
Current (mA)
0.8
0.6
85 C
0.4
0.2
0 0 0.2 0.4 0.6 0.8 1 VOH (V) 1.2 1.4 1.6 1.8 2
Figure 113. I/O (VCC = 5V)
RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 5V 16 14 12 10 8 6 4 2 0 0 1 2 3 VOL (V) 4 5 6
-40 C 25 C 85 C
186
ATtiny2313/V
2543F-AVR-07/04
Current (mA)
ATtiny2313/V
Figure 114. I/O (VCC = 2.7V)
RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 2.7V 4.5 4 3.5 3
-40 C 25 C 85 C
Current (mA)
2.5 2 1.5 1 0.5 0 0 1 2 3 VOL (V) 4 5 6
Figure 115. I/O (VCC = 1.8V)
RESET I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE
Vcc = 1.8V 1.4
-40 C 25 C 85 C
1.2
1
Current (mA)
0.8
0.6
0.4
0.2
0 0 0.2 0.4 0.6 0.8 VOL (V) 1 1.2 1.4 1.6 1.8
187
2543F-AVR-07/04
Figure 116. I/O VCC (VIH, I/O "1")
I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc
VIH, IO PIN READ AS '1' 3 85 C 25 C -40 C
2.5
2 Threshold (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 Vcc (V) 4 4.5 5 5.5
Figure 117. I/O VCC (VIL, I/O "0")
I/O PIN INPUT THRESHOLD VOLTAGE vs. Vcc
VIL, IO PIN READ AS '0' 3 85 C 25 C -40 C
2.5
2 Threshold (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 Vcc (V) 4 4.5 5 5.5
188
ATtiny2313/V
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ATtiny2313/V
Figure 118. I/O VCC
I/O PIN INPUT HYSTERESIS vs. VCC
0.7
0.6
85 C 25 C -40 C
0.5
Input Hysteresis (V)
0.4
0.3
0.2
0.1
0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 119. Reset I/O VCC (VIH,Reset "1")
RESET I/O INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
3
2.5
85 C 25 C -40 C
2
Threshold (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
189
2543F-AVR-07/04
Figure 120. Reset I/O VCC (VIL,Reset "0")
RESET I/O INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
2.5
2
85 C 25C -40 C
Threshold (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 121. Reset I/O VCC
RESET I/O INPUT PIN HYSTERESIS vs. VCC
0.8 0.7 0.6
Threshold (V)
85 C 25 C -40 C
0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
190
ATtiny2313/V
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ATtiny2313/V
Figure 122. Reset VCC (VIH,Reset "1")
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
2.5
85 C 25 C -40 C
2
Frequency (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 123. Reset VCC (VIL,Reset "0")
RESET INPUT THRESHOLD VOLTAGE vs. V CC
VIL, IO PIN READ AS '0'
2.5
2
85 C 25 C -40 C
Frequency (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
191
2543F-AVR-07/04
Figure 124. Reset VCC
RESET INPUT PIN HYSTERESIS vs. VCC
0.7 0.6 0.5
Frequency (V)
0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
-40 C 25 C 85 C
BOD
Figure 125. BOD (BOD 4.3V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 4.3V 4.45
Rising VCC
4.4
Threshold (V)
4.35
Falling VCC
4.3
4.25 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
192
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Figure 126. BOD (BOD 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 2.7V
2.85
Rising VCC
2.8
Threshold (V)
2.75
2.7
Falling VCC
2.65 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
Figure 127. BOD (BOD 1.8V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 1.8V
1.88
Rising VCC
1.86
Threshold (V)
1.84
1.82
Falling VCC
1.8
1.78 -60 -40 -20 0 20 Temperature (C) 40 60 80 100
193
2543F-AVR-07/04
Figure 128. VCC
BANDGAP VOLTAGE vs. OPERATING VOLTAGE
1.275
1.27
85 C -40 C
Bandgap Voltage (V)
1.265
25 C
1.26
1.255
1.25 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 129. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. VCC
104 103 102 101
FRC (KHz)
-40 C 25 C
100 99 98 97 96
85 C
95 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
194
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Figure 130.
WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE
105 104 103 102
FRC (KHz)
101 100 99 98 97 96 -60 -40 -20 0 20 Temperature 40 60 80 100
1.8 V 2.7 V
4.0 V
5.5 V
Figure 131. 8 MHz RC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
8.4 8.3 8.2
FRC (MHz)
5.5 V 4.0 V 2.7 V 1.8 V
8.1 8 7.9 7.8 7.7 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C)
195
2543F-AVR-07/04
Figure 132. 8 MHz RC VCC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. Vcc
9
8.5
-40 C 25 C 85 C
8
FRC (MHz)
7.5
7
6.5
6 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 133. 8 MHz RC Osccal
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
16 14 12 10
FRC (MHz)
8 6 4 2 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE
196
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Figure 134. 4 MHz RC l
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
4.2 4.15 4.1
FRC (MHz)
5.5 V 4.0 V 2.7 V 1.8 V
4.05 4 3.95 3.9 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 Temperature (C)
Figure 135. 4 MHz RC VCC
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. Vcc
4.2
-40 C
4.1
25 C
4
85 C
FRC (MHz)
3.9 3.8 3.7 3.6 3.5 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
197
2543F-AVR-07/04
Figure 136. 4 MHz RC Osccal
CALIBRATED 4MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
8 7 6 5
FRC (MHz)
4 3 2 1 0 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE
Figure 137. BOD VCC
BROWNOUT DETECTOR CURRENT vs. VCC
25
20
-40 C 25 C 85 C
15
ICC (uA)
10 5 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
198
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Figure 138. VCC
ANALOG COMPARATOR CURRENT vs. VCC
100 90 80 70 60
85 C 25 C -40 C
ICC (uA)
50 40 30 20 10 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
Figure 139. VCC
Programming Current vs. VCC
9 8 7 6
-40 C
25 C 85 C
ICC (mA)
5 4 3 2 1 0 2.5 3 3.5 4 VCC (V) 4.5 5 5.5
199
2543F-AVR-07/04
Figure 140. VCC (0.1 - 1.0 MHz )
RESET SUPPLY CURRENT vs. V CC
0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 4.5 4 3.5 3
5.5 V 5.0 V 4.5 V 4.0 V 3.6 V 3.3 V 3.0 V 2.7 V
ICC (mA)
2.5 2 1.5 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Frequency (MHz)
Figure 141. VCC (1 - 20 MHz )
RESET SUPPLY CURRENT vs. VCC
1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 40 35 30 25
5.5 V 5.0 V 4.5 V 4.0 V
ICC (mA)
20 15 10 5 0 0 2 4 6 8 10 12 14 16 18 20 Frequency (MHz)
3.6 V 3.3 V 3.0 V 2.7 V
200
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Figure 142. VCC
MINIMUM RESET PULSE WIDTH vs. V CC
2500
2000
Pulsewidth (ns)
1500
1000
500
85 C 25 C -40 C
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
201
2543F-AVR-07/04
0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (ox42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
SREG SPL OCR0B GIMSK EIFR TIMSK TIFR SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL TCCR0A TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL CLKPR ICR1H ICR1L GTCCR TCCR1C WDTCSR PCMSK EEAR EEDR EECR PORTA DDRA PINA PORTB DDRB PINB GPIOR2 GPIOR1 GPIOR0 PORTD DDRD PIND USIDR USISR USICR UDR UCSRA UCSRB UBRRL ACSR UCSRC UBRRH DIDR
7
I - SP7 INT1 INTF1 TOIE1 TOV1 - PUD - FOC0A - COM0A1 COM1A1 ICNC1
6
T - SP6 INT0 INTF0 OCIE1A OCF1A - SM1 - FOC0B CAL6 COM0A0 COM1A0 ICES1
5
H - SP5 PCIE PCIF OCIE1B OCF1B - SE - - CAL5 COM0B1 COM1B1 -
4
S - SP4 - - - - CTPB SM0 - - CAL4 COM0B0 COM1BO WGM13
3
V - SP3 - - ICIE1 ICF1 RFLB ISC11 WDRF WGM02 T/C0 (8 ) CAL3 - - WGM12
2
N - SP2 - - OCIE0B OCF0B PGWRT ISC10 BORF CS02 CAL2 - - CS12
1
Z - SP1 - - TOIE0 TOV0 PGERS ISC01 EXTRF CS01 CAL1 WGM01 WGM11 CS11
0
C - SP0 - - OCIE0A OCF0A SELFPRGEN ISC00 PORF CS00 CAL0 WGM00 WGM10 CS10
7 10 73 58 59 74, 102 74 147 73 51 35 72 73 25 69 97 100 101 101 101 101 102 102
T/C0 B
T/C0 A
T/C1 - T/C1 - T/C1 - A T/C1 - A T/C1 - B T/C1 - B - CLKPCE - - - - - - - CLKPS3 - CLKPS2 - CLKPS1 - CLKPS0
27 102 102
T/C1 - T/C1 - - FOC1A WDIF PCINT7 - - - - - - PORTB7 DDB7 PINB7 - - - - PORTB6 DDB6 PINB6 EEPM1 - - - PORTB5 DDB5 PINB5 EEPM0 - - - PORTB4 DDB4 PINB4 - FOC1B WDIE PCINT6 - - - WDP3 PCINT5 - - - WDCE PCINT4 - - - WDE PCINT3 - EEPROM EEPROM EERIE - - - PORTB3 DDB3 PINB3 EEMPE PORTR2 DDA2 PINA2 PORTB2 DDB2 PINB2 EEPE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 - - WDP2 PCINT2 - - - WDP1 PCINT1 - PSR10 - WDP0 PCINT0 -
76 100 40 59 15 16 16 56 56 56 56 56 56 20 20 20
I/O 2 I/O 1 I/O 0 - - - USISIF USISIE RXC RXCIE ACD - - - - - - - - PORTD6 DDD6 PIND6 USIOIF USIOIE TXC TXCIE ACBG - - - - UMSEL - - - PORTD5 DDD5 PIND5 USIPF USIWM1 UDRE UDRIE ACO - - - - UPM1 - - - PORTD4 DDD4 PIND4 USIDC USIWM0 FE RXEN ACI - - - - UPM0 - - - - - - - PORTD3 DDD3 PIND3 USICNT3 USICS1 DOR TXEN UBRRH[7:0] ACIE - - - - USBS PORTD2 DDD2 PIND2 USICNT2 USICS0 UPE UCSZ2 ACIC - - - - UCSZ1 UBRRH[11:8] AIN1D - AIN0D - PORTD1 DDD1 PIND1 USICNT1 USICLK U2X RXB8 ACIS1 - - - - UCSZ0 PORTD0 DDD0 PIND0 USICNT0 USITC MPCM TXB8 ACIS0 - - - - UCPOL
56 56 56 137 137 138 121 122 124 126 141
USI
UART (8 )
125 126 142
202
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
Note: 1. "0" I/O 2. SBI CBI 0x00 - 0x1F I/O SBIS SBIC 3. "1" AVR CBI SBI CBI SBI 0x00 - 0x1F 4. I/OINOUT 0x00 - 0x3FI/O LD ST I/O 0x20
203
2543F-AVR-07/04
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd k k 1 2 (Z) (Z) Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k P,b P,b Rd Rd Rd "0" "1" I/O "0" I/O "1" "1" "0" "1" "0" "1" "0" T "1" T "0" "1" "0" I/O I/O Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd 0xFF - Rd Rd 0x00 - Rd Rd Rd v K Rd Rd * (0xFF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd 0xFF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 2 2 1 1 1

#
RJMP IJMP RCALL ICALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID
SBI CBI LSL LSR ROL
204
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH Rd Rd Rd s s Rr, b Rd, b
T T 2 2 SREG T SREG T SREG SREG Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr Rd, Z Rd, Z+ Rd, P P, Rr Rr Rd
Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK
Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
#
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2 1 1 1 N/A
MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP
SRAM SRAM I/O I/O
MCU
NOP SLEEP WDR BREAK ( Sleep specific) ( WDR/timer specific) None None None
205
2543F-AVR-07/04
(MHz) ATTINY2313V-10PI ATTINY2313V-10PJ(2) ATTINY2313V-10SI ATTINY2313V-10SJ(2) ATtiny2313-20PI ATtiny2313-20PJ(2) ATtiny2313-20SI ATtiny2313-20SJ(2) (1) 20P3 20P3 20S 20S 20P3 20P3 20S 20S (-40C 85C)
10(3)
1.8 - 5.5V
20(3)
2.7 - 5.5V
(-40C 85C)
Note:
1. wafer Atmel 2. 3. P170Figure 81 P170Figure 82
20P3 20S 20 0.300" PDIP 20 0.300" SOIC
206
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
20P3
D
PIN 1
E1
A
SEATING PLANE
L B1 e E B
A1
C eC eB
SYMBOL A A1 D E E1 B Notes: 1. This package conforms to JEDEC reference MS-001, Variation AD. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB eC e
COMMON DIMENSIONS (Unit of Measure = mm) MIN - 0.381 25.493 7.620 6.096 0.356 1.270 2.921 0.203 - 0.000 NOM - - - - - - - - - - - MAX 5.334 - 25.984 8.255 7.112 0.559 1.551 3.810 0.356 10.922 1.524 Note 2 Note 2 NOTE
2.540 TYP
1/12/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 20P3 REV. C
R
207
2543F-AVR-07/04
20S
C
1
EH
N
Top View
A1
End View
COMMON DIMENSIONS (Unit of Measure = inches)
e
b A D
SYMBOL
MIN
L
NOM
MAX
NOTE
A A1 b C D
0.0926 0.0040 0.0130 0.0091 0.4961 0.2914 0.3940 0.0160 0.050 BSC
0.1043 0.0118 0.0200 0.0125 0.5118 0.2992 0.4190 0.050 3 1 2 4
Side View
E H L e
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information. 2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006") per side. 3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010") per side. 4. "L" is the length of the terminal for soldering to a substrate. 5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm 1/9/02 (0.024") per side.
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 20S2, 20-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC)
DRAWING NO. 20S2
REV. A
208
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
ATtiny2313 Rev B
ATtiny2313 * * * 1. 2.7 V EEPROM 0x00 0xFF 2. - - (SPIEN ) (RSTDISBL )
3.
ATtiny2313 Rev A
A
209
2543F-AVR-07/04
ATtiny2313
Rev. 2514E-04/04 Rev. 2514F-07/04
1. 2. 3. 4. 5. 6. 7. 8. 9.
P1" " P51" B " P152" " P152Table 69 P152Table 70 P152" " P164" " P165Table 78 P168" " P171"ATtiny2313 " PCINT15 PCINT7, EEMWE EEMPE EEWE EEPE
Rev. 2514D-03/04 Rev. 2514E-04/04
1.
2. 3. 4. 5.
- 12MHz 10MHz - 24MHz 20MHz P2Figure 1 P206" " P170" VCC " P171"ATtiny2313 "
Rev. 2514C-12/03 Rev. 2514D-03/04
1. 2. 3. 4. 5. 6. 7. 8. 9.
P21Table 2 P37" " P170" VCC " P164" " P198Figure 137 mA A P206" " MLF P207"20P3" C SPMEN to SELFPRGEN
Rev. 2514B-09/03 Rev. 2514C-12/03 Rev. 2514A-09/03 Rev. 2514B-09/03
1.
P24" RC "
1. 2. 3. 4. 5.
UART USARTP1"" P2" " P32Table 15 P169Table 80 P164" " 5 P168" "
210
ATtiny2313/V
2543F-AVR-07/04
ATtiny2313/V
6. 7. 8. 9. P170Figure 81 P170Figure 82 P202" " SFIOR GTCCR P206" " P209" "
211
2543F-AVR-07/04
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
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Regional Headquarters
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ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems.
Printed on recycled paper.
2543F-AVR-07/04

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